In functional/timing simulation, the LOCKED signal does not go high for cascaded DCM design with the following configuration:
- CLKDV output of first DCM is connected to CLKIN of second DCM.
- LOCKED signal of first DCM is connected to second DCM via inverter.
This is an intended behavior. To ensure that a DCM starts the locking process correctly after a reset, the RST signal must be released only after three stable clock cycles are received by the DCM.
In the cascaded DCM configuration, the LOCKED signal of the first DCM is connected to the RST input of the second DCM. This ensures the second DCM to be in RST until the first DCM has locked with a stable clock.
This configuration works correctly for the majority of cascading schemes except when CLKDV of the first DCM is used as the CLKIN of the second DCM. The reason for this is that CLKDV does not toggle until LOCKED is high. Since the RST is released at LOCKED, and the second DCM has not received three stable clock cycles before its RST is released, the second DCM might not have LOCKED properly.
In the simulation model, the second DCM will not lock.
To ensure proper LOCKED status, please insert an SRL with tree shift registers or three registers in series between inverted LOCKED and RST. The SRL or registers should be clocked by the CLKIN of the second DCM (CLKDV of the first DCM).
This will delay the release of RST by three clock cycles after the LOCKED status of the first DCM is high, thus ensuring the second DCM receives three stable clock cycles before its reset is released.
The additional delay/register will be inserted in the Clocking Wizard in the ISE 8.1i (next major release of ISE).