What is the size of the replay buffer? How many transmit buffers are available?
In the LogiCORE Endpoint for PCI Express targeting Virtex-4 and Virtex-II Pro and the LogiCORE Endpoint PIPE for PCI Express for the Spartan family, there is no separate Replay Buffer in the Data Link Layer.
The core contains a set of transmit buffers in the transaction layer which also act as the replay buffer. The core holds the packets in the transmit buffers until it gets an acknowledgement DLLP (ACK or NAK) from the other end. If a packet needs to be replayed, it will be transmitted again out of these buffers. If the buffers fill up, the core prevents more data from passing into the core by de-asserting trn_tdst_rdy_n. The trn_tbuf_av bus output of the core informs the user how many buffers are vacant at any given time.
Please refer to the User Guide (UG185) for the PCI Express Core for more information on the size of the buffers and how many are available. Please see the section titled "Transmit Buffers" in Chapter 5, "Designing with the Core." The UG is delivered with the core by CORE Generator in the doc directory.
These buffers are shared between the user application and packets that are produced internally by the cores configuration management module (CMM). The CMM generates completion TLPs in response to configuration transactions, error messages, and interrupt requests when requested by the user application. These packets are inserted into the same transaction layer transmit buffers as packets coming from the user application. When this happens, the core will briefly deassert trn_tdst_rdy_n as a packet is loaded into the transmit buffer from the CMM to ensure the user does not attempt to put a packet in the core at the same time. Please refer to the section titled "Destination Throttling of the Endpoint Transaction Transmit Interface" in Chapter 5 of the PCI Express User Guide for more information on this behavior.