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AR# 19039

LogiCORE SPI-4.2 (POS-PHY L4) v6.1 - Migrating from v6.0.1 to v6.1(Migration Guide) on Dual SPI-4.2 design

Description

General Description:  

This Answer Record describes additional steps needed to migrate from v6.0 to v6.1 of the dual SPI-4.2 design. 

 

Please see (Xilinx Answer 18903) and follow the steps mentioned in Answer 18903 prior to continuing with this document.

Solution

A number of constraints were changed in v6.1 that ease the implementation of a dual core solution. When migrating from v6.0 to v6.1, only users which intend to implement two SPI-4.2 cores in 1 device need to follow the directions below. The following changes ensure that the two SPI-4.2 cores have unique constraints. Note that the text in bold indicates the portion of the constraint that must be edited. The following examples are done for a 700Mbps implementation of the Core. 

 

The following changes are required to migrate the Static Alignment Sink Core to v6.1: 

 

1. pl4_snk_top1 globally replaces pl4_snk_top0 

2. CalClk_bufg1 globally replaces CalClk_bufg0 

3. LoopbackClk_bufg1 globally replaces LoopbackClk_bufg0 

4. 

NET "CalClk" TNM_NET = "CalClk_east";  

TIMESPEC "TS_CalClk_east" = PERIOD "CalClk_east" 100 MHz HIGH 50 %; 

replaces  

NET "CalClk" TNM_NET= "CalClk"; 

TIMESPEC "TS_CalClk" = PERIOD "CalClk" 100 MHz HIGH 50 %; 

5. 

NET "LoopbackClk" TNM_NET = "LoopbackClk_east"; 

TIMESPEC "TS_LoopbackClk_east" = PERIOD "LoopbackClk_east" 175 MHz HIGH 50 %; 

replaces 

NET "LoopbackClk" TNM_NET = "LoopbackClk"; 

TIMESPEC "TS_LoopbackClk" = PERIOD "LoopbackClk" 175 MHz HIGH 50 %; 

6. 

NET "RDClk_P" TNM_NET = "RDClk_P_east"; 

TIMESPEC "TS_RDClk_P_east" = PERIOD "RDClk_P_east" 351 MHz HIGH 50 %; 

replaces 

NET "RDClk_P" TNM_NET = "RDClk_P"; 

TIMESPEC "TS_RDClk_P" = PERIOD "RDClk_P" 351 MHz HIGH 50 %; 

7. 

 #NET "SnkCalClk" TNM_NET = "SnkCalClk_east"; 

 #TIMESPEC "TS_SnkCalClk_east" = PERIOD "SnkCalClk_east" 175 MHz HIGH 50 %; 

replaces 

 #NET "SnkCalClk" TNM_NET = "SnkCalClk"; 

 #TIMESPEC "TS_SnkCalClk" = PERIOD "SnkCalClk" 175 MHz HIGH 50 %; 

8. 

 #NET "SnkFFClk" TNM_NET = "SnkFFClk_east"; 

 #TIMESPEC "TS_SnkFFClk_east" = PERIOD "SnkFFClk_east" 175 MHz HIGH 50 %; 

replaces  

 #NET "SnkFFClk" TNM_NET = "SnkFFClk"; 

 #TIMESPEC "TS_SnkFFClk" = PERIOD "SnkFFClk" 175 MHz HIGH 50 %; 

9. 

 #NET "SnkStatClk" TNM_NET = "SnkStatClk_east"; 

 #TIMESPEC "TS_SnkStatClk_east" = PERIOD "SnkStatClk_east" 175 MHz HIGH 50 %; 

replaces 

 #NET "SnkStatClk" TNM_NET = "SnkStatClk"; 

 #TIMESPEC "TS_SnkStatClk" = PERIOD "SnkStatClk" 175 MHz HIGH 50 %; 

10. 

NET "pl4_snk_top1/pl4_snk_clk0/snkclk_dcmo" TNM_NET = "RDClkDiv_GP_east"; 

TIMESPEC "TS_RDClkDiv_GP_east" = PERIOD "RDClkDiv_GP_east" "TS_RDClk_P_east" / 2; 

replaces  

NET "pl4_snk_top0/pl4_snk_clk0/snkclk_dcmo" TNM_NET = "RDClkDiv_GP"; 

TIMESPEC "TS_RDClkDiv_GP" = PERIOD "RDClkDiv_GP" "TS_RDClk_P" / 2; 

11. 

NET "pl4_snk_top1/RDClk0_GP" TNM_NET = "RDClk0_GP_east"; 

TIMESPEC TS_ClkDiv_Clk0_east = FROM : RDClkDiv_GP_east : TO : RDClk0_GP_east : TS_RDClk_P_east ; 

replaces  

NET "pl4_snk_top0/RDClk0_GP" TNM_NET = "RDClk0_GP"; 

TIMESPEC TS_ClkDiv_Clk0 = FROM : RDClkDiv_GP : TO : RDClk0_GP : TS_RDClk_P ; 

12. 

INST pl4_snk_top1 AREA_GROUP = AG_pl4_snk_east ; 

AREA_GROUP "AG_pl4_snk_east" RANGE = SLICE_X46Y86:SLICE_X90Y159 ; 

replaces  

INST pl4_snk_top0 AREA_GROUP = AG_pl4_snk ; 

AREA_GROUP "AG_pl4_snk" RANGE = SLICE_X46Y86:SLICE_X90Y159 ; 

 

In addition to the changes above, the following changes are required to migrate the Dynamic Alignment Sink Core to v6.1: 

 

1. 

TIMEGRP RDClkDiv_Except_RAM_east = "RDClkDiv_GP_east" EXCEPT "RAMS" ; 

replaces 

TIMEGRP RDClkDiv_Except_RAM = "RDClkDiv_GP" EXCEPT "RAMS" ; 

2. 

TIMESPEC TS_RD_IO_east = FROM : RDClk_P_east : TO : RDClkDiv_Except_RAM_east: TS_RDClk_P_east ; 

replaces 

TIMESPEC TS_RD_IO = FROM : RDClk_P : TO : RDClkDiv_Except_RAM : TS_RDClk_P ; 

3. 

NET "pl4_snk_top1/RDClk0_GP" TNM_NET = "RDClk0_GP_east"; 

TIMESPEC TS_ALIGN_REQ_east = FROM : RDClkDiv_GP_east : TO : RDClk0_GP_east : TS_RDClk_P_east ; 

replaces 

NET "pl4_snk_top0/RDClk0_GP" TNM_NET = "RDClk0_GP"; 

TIMESPEC TS_ALIGN_REQ = FROM : RDClkDiv_GP : TO : RDClk0_GP : TS_RDClk_P ; 

 

The following changes are required to migrate the Source Core to v6.1: 

 

1. pl4_src_top1 globally replaces pl4_src_top0 

2. If slave clocking is selected: pl4_src_clk1 globally replaces pl4_src_clk0 

3.  

NET "SysClk_P" TNM_NET = "SysClk_P_east"; 

TIMESPEC "TS_SysClk_P_east" = PERIOD "SysClk_P_east" 350 MHz HIGH 50 %; 

replaces  

NET "SysClk_P" TNM_NET = "SysClk_P"; 

TIMESPEC "TS_SysClk_P" = PERIOD "SysClk_P" 350 MHz HIGH 50 %; 

4. 

NET "pl4_src_top1/TSClk_GP" TNM_NET = "TSClk_GP_east"; 

TIMESPEC "TS_TSClk_GP_east" = PERIOD "TSClk_GP_east" 88 MHz HIGH 50% ; 

replaces 

NET "pl4_src_top0/TSClk_GP" TNM_NET = "TSClk_GP"; 

TIMESPEC "TS_TSClk_GP" = PERIOD "TSClk_GP" 88 MHz HIGH 50% ; 

5. 

 #NET "SrcCalClk" TNM_NET = "SrcCalClk_east"; 

 #TIMESPEC "TS_SrcCalClk_east" = PERIOD "SrcCalClk_east" 175 MHz HIGH 50 %; 

replaces 

 #NET "SrcCalClk" TNM_NET = "SrcCalClk"; 

 #TIMESPEC "TS_SrcCalClk" = PERIOD "SrcCalClk" 175 MHz HIGH 50 %; 

6. 

 #NET "SrcFFClk" TNM_NET = "SrcFFClk_east"; 

 #TIMESPEC "TS_SrcFFClk_east" = PERIOD "SrcFFClk_east" 175 MHz HIGH 50 %; 

replaces 

 #NET "SrcFFClk" TNM_NET = "SrcFFClk"; 

 #TIMESPEC "TS_SrcFFClk" = PERIOD "SrcFFClk" 175 MHz HIGH 50 %; 

7. 

 #NET "SrcStatClk" TNM_NET = "SrcStatClk_east"; 

 #TIMESPEC "TS_SrcStatClk_east" = PERIOD "SrcStatClk_east" 175 MHz HIGH 50 %; 

replaces 

 #NET "SrcStatClk" TNM_NET = "SrcStatClk"; 

 #TIMESPEC "TS_SrcStatClk" = PERIOD "SrcStatClk" 175 MHz HIGH 50 %; 

8. 

INST pl4_src_top1 AREA_GROUP = AG_pl4_src_east ; 

AREA_GROUP "AG_pl4_src_east" RANGE = SLICE_X46Y12:SLICE_X91Y63 ; 

replaces 

INST pl4_src_top0 AREA_GROUP = AG_pl4_src ; 

AREA_GROUP "AG_pl4_src" RANGE = SLICE_X46Y12:SLICE_X91Y63 ;

AR# 19039
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article