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AR# 19064

6.2i XST - XST handles Verilog parameters incorrectly when a slice of the parameter is used and has the direction [0:n]


Keywords: Verilog, MSB, LSB, swaps, parameter

Urgency: Standard

General Description:
If a module has a parameter that is described as follows:

parameter [0:9] MyParam = 10'b0000010000;

and it is used as follows:

.input_port (MyParam[0:7]), // I [0:7]

XST will shift the slice from 0:7 to 2:9 so that input_port is now is tied to the following constant:



The only known way to work around this issue is to use the [n:0] notation instead.

This problem has been fixed in the latest 6.2i Service Pack available at:
The first service pack containing the fix is 6.2i Service Pack 2.
AR# 19064
Date 07/18/2007
Status Archive
Type General Article
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