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AR# 19078

7.1i XST - Using SET constraints with XST to create relationally placed macros (RPMs) in HDL

Description

Keywords: U_SET, H_SET, RLOC, LOC

Starting with XST version 6.3isp1, XST can now pass set names to facilitate the creation of relationally placed macros (RPMs). For more information on the various SET constraints, refer to the Constraints Guide, which can be accessed at:
http://support.xilinx.com/support/software_manuals.htm

Solution

1

VHDL

The following VHDL code represents a very simple RPM in VHDL using SET names.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ffs is
Port ( d : in std_logic_vector(7 downto 0);
clk : in std_logic;
q : out std_logic_vector(7 downto 0));
end ffs;

architecture ffs_arch of ffs is

signal reg_1 : std_logic_vector (3 downto 0);
signal reg_2 : std_logic_vector (3 downto 0);

attribute rloc : string;
attribute rloc of reg_1 : signal is "X1Y16 X1Y16 X0Y14 X0Y14";
attribute rloc of reg_2 : signal is "X1Y16 X1Y16 X0Y14 X0Y14";

attribute u_set : string;
attribute u_set of reg_1 : signal is "reg1_set";
attribute u_set of reg_2 : signal is "reg2_set";

begin

process (clk) is
begin
if clk'event and clk = '1' then
reg_1 <= d(3 downto 0);
reg_2 <= d(7 downto 4);
end if;
end process;

q (3 downto 0) <= reg_1;
q (7 downto 4) <= reg_2;

end ffs_arch;

2

Verilog

The following Verilog code represents a very simple RPM in Verilog using SET names.

module ffs (d,clk,q);
input [7:0] d;
input clk;
output [7:0] q;

(* RLOC = "X1Y16 X1Y16 X0Y14 X0Y14" *)
(* U_SET = "reg1_set" *)
reg [3:0] reg_1;

(* RLOC = "X1Y16 X1Y16 X0Y14 X0Y14" *)
(* U_SET = "reg2_set" *)
reg [3:0] reg_2;

always @(posedge clk)
begin
reg_1 <= d[3:0];
reg_2 <= d[7:4];
end

assign q[3:0] = reg_1;
assign q[7:4] = reg_2;

endmodule
AR# 19078
Date Created 09/03/2007
Last Updated 01/07/2009
Status Archive
Type General Article