General Description: In some cases, XST swaps bits in unconstrained arrays when assignments are made. In VHDL, it is legal to leave an array unconstrained if the array can obtain its bounds from the signal that is sourcing it. An unconstrained array is a signal that does not have an upper or lower bound, as in the following example:
signal register_out : std_logic_vector ; -- there is no range, for example (15 downto 0)
If possible, constrain the arrays in your design to verify if they are the point of failure.