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AR# 19194

6.2i XST - My EDK designs are incorrectly counting the address for caches when using the PLB IP interfaces

Description

Keywords: PPC, IPIF, count, line, access

Urgency: Urgent

General Description:
When a data cache flush command is issued when using burst cache-line support, the data appears to be invalid.

In the attached failure case (see the attached MTI simulation force file "addr_cntr_sim.do"), the "reg_addr_plus_n" register is loaded with 0x0200 as the result of an input address of 0x80000200. The "incr_value" is set to 0x8 as a result of the "input addr_cnt_size" being set to 0x2. After the address load is commanded, the output of the ALU (addr_plus_n) should be 0x0208, but instead it is 0x00FC.

Solution

This problem first appears in 6.2i. XST is generating incorrect logic for the LB core. You can work around this issue, by disabling the cache-line burst support as follows:

C_INCLUDE_BURST_CACHELN_SUPPORT=0

You can obtain service pack updates for the ISE software from:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=sp

To install the patch, follow these steps:
1. Rename the old files in directory "$XILINX/bin/platform" as follows:
NT: xst.exe to xst_old.exe, libxst.dll to libxst_old.dll
Unix/Linux: xst to xst_old, libxst.so to libxst_old.so

2. Extract the archive to the "$XILINX" directory:

6.2i

http://www.xilinx.com/txpatches/pub/swhelp/ise6_updates/62i_xst_patch.zip

6.2i SP1

http://www.xilinx.com/txpatches/pub/swhelp/ise6_updates/62isp1_xst_patch.zip

6.2i SP2

http://www.xilinx.com/txpatches/pub/swhelp/ise6_updates/62isp2_xst_patch.zip

This problem has been fixed in the latest 6.2i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.2i Service Pack 3.
AR# 19194
Date Created 03/24/2004
Last Updated 04/09/2007
Status Archive
Type General Article