We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 19225

7.1i CORE Generator - Simulating a Verilog design including an IP Core might produce: "Warning: (vsim-3722) <core_wrapper>.v(4193): [TFMPC] -Missing connection for port 'Q'."


Keywords: IP, Core, Verilog, SoB, Structures of Behavior, simulation, ModelSim

When simulating certain IP cores created with Core Generator , ModelSim produces multiple warnings similar to the following:

"# ** Warning: (vsim-3722) top/cordic_mod.v(4193): [TFMPC] - Missing connection for port 'Q'."


Currently, components used in the SoB (Structures of Behaviors) Verilog behavioral models for some cores do not specify all of the ports in the instantiation. This leads to the 'TFMPC' warnings during simulation.

The omissions were intentional and can be ignored.

This problem (generation of multiple warnings) has been corrected in the ISE 8.1i release by adding all unconnected ports to the port instantiations in the SoB Verilog behavioral models. Unconnected ports will be followed by an open and close parentheses.

AR# 19225
Date 12/12/2006
Status Archive
Type General Article