I created a simple design with an input pad feeding a FF. I created a TIMESPEC to cover the path FROM the PAD to the FF. However, when I look at the reports generated by the tools, I see a discrepancy. PAR reports that there is 1 level of logic, and Timing reports that there are 0 levels of logic. Why does this happen?
This is a problem with how TRCE calculates this number. The PAR report is correct in this instance.
This will be fixed in the next major software release.