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General Description: To perform timing or post-synthesis functional HDL simulation in M1, the Verilog and/or VHDL (VITAL) SimPrim models must be compiled for use in the Model Technology simulator. If instantiated LogiBLOX and/or Unified library components are to be behaviorally simulated, the LogiBLOX and/or UniSim libraries must be compiled, as well.
This Answer Record is written for the ModelSim versions 5.1x for Workstations, or 4.7x for PCs. It applies to earlier versions of the simulator if the word MODELSIM is replaced with V-SYSTEM.
Please see (Xilinx Answer 2561) for information on how to compile the HDL libraries for Xilinx Alliance 2.1.
A TCL script is available on Xilinx FTP site. Currently, this script can only be used with the ModelSim EE/PE edition.
NOTE: You must use the xilinx_lib.tcl script for ModelSim EE, and xilinx_lib.tcl for ModelSim PE.