When I change the parameters of the DDS to increase the output bit width, I see that the output waveform becomes noisy. When the output bit width is low, I see a repeating sequence of values representing a sine wave. When the output bit width increases, the sequence of values starts to become random.
What causes this?
The output bit width is dependent on the SFDR (spurious free dynamic range) parameter. When this parameter is increased past 84 dB, the core must use noise reduction, either phase dithering or Taylor Series, in order to meet the SFDR requirement. The CORE Generator GUI will automatically select 'Auto' for noise shaping. This will result in a small amount of noise being mixed in with the look up table address and cause the output values to vary slightly. In many applications, noise shaping is tolerable and desired in order to increase SFDR without greatly increasing FPGA resource usage.
A CR has been filed as an enhancement request to have more control over the noise shaping option.