We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19330

6.2 EDK - ChipScope VIO core errors out during synthesis


Keywords: VIO, ChipScope, XST, error

Urgency: Standard

General Description:

When I use a ChipScope VIO core that utilizes the "sync_out" port, XST issues a compilation error.



To resolve this issue, edit the "chipscope_vio_v2_1_0.tcl" file as follows:

1. The ".tcl" file is located here:


2. Make the following change at line 181:

Change the following:

if { $params(C_SYNC_OUTPUT_ENABLE) > 0 } {
puts $hdl_file "sync_out => sync_in,"
set clk_needed 1

to this:

if { $params(C_SYNC_OUTPUT_ENABLE) > 0 } {
puts $hdl_file "sync_out => sync_out,"
set clk_needed 1


This problem is fixed in the latest 6.2 EDK Service Pack, available at:
The first service pack containing the fix is EDK 6.2 Service Pack 2.
AR# 19330
Date 04/09/2007
Status Archive
Type General Article
Page Bookmarked