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AR# 19337

ChipScope Pro Analyzer - "INFO: Found 0 Core Units in the JTAG device Chain"


When I run ChipScope Analyzer tool, it does not find a core unit, and the following error occurs:

"INFO: Found 0 Core Units in the JTAG device Chain"

Why does this occur?


There are a number of reasons why the ChipScope Analyzer tool might not be able to find the core units. ChipScope Analyzer software polls the JTAG chain for a status word that will tell it the number and type of cores in the device. It can be affected either by JTAG noise or a core timing issue in the design that affects the core. These might corrupt the status word that is read out. Following are some issues to check for:

Solution 1

The core is not correctly implemented, or not present at all. To verify this, perform the following steps:

1. Open the FPGA Editor (after Place and Route) to edit your design.

2. Go to "Tools" and "ILA." A window is displayed that lists all of the probed signals. If an error message appears specifying, "There is no ILA Core," your design does not contain a ChipScope Core. You might have to go back to your design and determine why the core was not implemented (the synthesis and translate reports can tell you if all of the netlists are correctly implemented, including the ChipScope ILA Core and the ICON Core).

If you can detect the core in FPGA Editor and you are using the CORE Generator flow, the following Synthesis and Implementation options might help:


-keep_hierarchy No
-read_cores No


Remove the -insert_keep_hierarchy option.



Solution 2

Programming the FPGA with iMPACT, instead of ChipScope Analyzer, can also solve the issue. Perform the following steps:

1. Run iMPACT, to program the FPGA.

2. Exit iMPACT.

3. Run ChipScope Analyzer.

Solution 3

If ChipScope Pro 6.2i is used, there is a known issue when a XCFxxP/Platform Flash is in the chain. See (Xilinx Answer 19578).

Solution 4

There is a known issue when the JTAG chain contains a System Ace MPM. The core unit might not be found. To work around the problem, put the following line in the ChipScope project file (.cpj) and read it in before opening the cable:


Replace the "X" with the position index number of the V50E device. Index 0 for the first device in the chain. Information messages about skipping scanning on the V50E device are placed in the ChipScope log.

To use the updated ".cpj" file, follow the steps listed in Solution 2 above. Be sure to load the ".cpj" file immediately after ChipScope Analyzer launches before any other action.

Solution 5

ChipScope Analyzer might not be able to find the core because the configuration options are not set correctly. If the BitGen option LCK_cycle (or Release DLL in Project Navigator) is not set to "Nowait," ChipScope Analyzer might not be able to detect the core because the ChipScope Core must be initialized with the release of GWE. Setting this option to "Nowait" (default option) might solve the issue.

Solution 6

If there are multiple FPGAs on the board with the DONE pins tied together, this error might occur in a situation where DONE is held Low by unconfigured devices and configuration does not fully complete. To work around this issue, ensure that all FPGAs on the board are configured or that the DriveDONE option is set for the target device.

Solution 7

Check that a PERIOD constraint has been added to the clock used as the Clock for your ILA. If there is no constraint on this net in the ISE software project, the ChipScope constraints will not be applied correctly and might result in the cores not being recognized.

Solution 8

Check your JTAG chain for non-Xilinx devices. You will need to enter the instruction register length for any non-Xilinx devices in the chain in the Analyzer GUI. To find this, you can examine the devices' BSDL file. There will be an entry similar to below:

attribute INSTRUCTION_LENGTH of <entity name> : entity is XX;

If you do not enter the Instruction Register length, the analyzer cannot set the JTAG offsets correctly and will not be able to identify the devices or ChipScope cores.

** If the non-Xilinx devices use the optional TRST JTAG pin then ChipScope Pro Analyzer requires that this pin is tied high.

Solution 9

The default JTAG TCK frequency might be set too high for the devices in the chain. This is sometimes set to 24 MHz. This will likely exceed the maximum TCK speed for devices in the chain as defined in the BSDL file or exacerbate any signal integrity issue on the JTAG lines. This can prevent the cores being recognized. When connecting to the cable, check the "Speed" setting in the cable connection dialog. 3 MHz is a safe value that will work for most chains.

To change the default setting for TCK, you need to edit the cs_analyzer.ini file. This will be located in the "C:\Documents and Settings\<username>\.chipscope" directory for Windows or th2 "$home\.chipscope" directory for Linux. To set the Default speed at 3 MHz, make the entry match the following:


openTarget.0=xilinx_platformusb PORT\=USB21 FREQUENCY\=3000000
AR# 19337
Date 02/25/2013
Status Active
Type General Article
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