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AR# 19347

6.2i CORE Generator - Release Notes and Known Issues for CORE Generator 6.2i IP Update 1.1


General Description:

This Answer Record contains the following:

- Release Notes and Installation Instructions

- What's New in 6.2i IP update 1.1

- A list of Known Issues for FIFO Generator v1.1


What's New

This IP Update contains FIFO Generator v1.0. This is the only new core released in this IP Update.

Installation Instructions and Required Tools

Supported Operating Systems

- Windows 2000 Professional (Service Pack 2-4)

- Windows XP Home (Service Pack 1)/Professional (Service Pack 1)

- Sun Solaris 8/9

- Red Hat Linux 7.3/8.0

Tool Requirements

Before you install the IP provided in this update, the 6.2i Xilinx ISE software with Service Pack 2 (6.2.02i) must be installed on your machine. Installing this version of the ISE software gives you access to the correct version of the CORE Generator application.

For information on the latest available CORE Generator IP updates, please see the Xilinx Software Updates page and follow the instructions for downloading and installing these updates:


Method 1: Automated Update using the Updates Installer

NOTE: You must be using ISE 6.2i to access the proper version of the Updates Installer, which automatically locates the required update file archive and displays it in the selection window. It is not necessary to perform a separate download of the update file archive using this method. You should also install ISE 6.2.02i software prior to installing IP Update 1.1.

1. Start the CORE Generator Update Installer by selecting Tools -> Update Installer from the CORE Generator main GUI. If you are prompted for a proxy host, contact your administrator to determine the proxy host address and port number that you should be using to get through your firewall.

2. Select " 6.2i IP Update 1" from the list of updates in the Available Packages panel.

3. Click "Add To Install Queue" to add the ZIP file for the update to the install queue. If you are prompted to enter a login name and a password, use the Xilinx login and password that you would normally use when downloading IP Updates and software Service Packs.

4. Click "Install All Packages From Queue" to automatically initiate a download of the update. After the update has been downloaded, the Updates Installer displays a dialog box indicating that it is terminating the CORE Generator session and installing the downloaded archive. Another dialog box informs you when the update installation is complete. You can then restart CORE Generator.

5. To confirm that you have installed the update properly, check the following file:


NOTE: This assumes that your Xilinx software is installed in C:\Xilinx.

Ensure that "gip1.1" is noted at the top of the file along with the current date and time.

Method 2: Manual Installation Method

1. Close the CORE Generator application if it is running.

2. Download the ZIP file (PC) or "tar.gz" file (UNIX) from the following location and save it to a temporary directory:


For Windows, unpack the ZIP file using WinZip 7.0 SR-1 or later.

For UNIX platforms, you can use some versions of UnZip to unpack this ZIP file. Xilinx recommends that you download the "tar.gz" file and unpack it using the UNIX command line utilities "gunzip" and "tar". WinZip and GNU "tar" are not recommended for extracting the "tar.gz" archive due to differences in the way they handle files with long path names. Please see (Xilinx Answer 11162) for more details.

3. Extract the ZIP file (62i_ip_update1_1.zip) or "tar.gz" (62i_ip_update1_1.tar.gz) archive to the root directory of your Xilinx software installation. Allow the extractor utility that you use to overwrite all existing files and maintain the directory structure pre-defined in the archive.

For PC, the Xilinx software installation directory is typically located at "C:\XILINX" if the installation defaults were used.

For UNIX, if you have already installed your Xilinx ISE software, the Xilinx installation directory location is the value of the "XILINX" variable, which is defined by your setup script. After sourcing your Xilinx setup script, type "echo $XILINX" to determine the location of your Xilinx installation. You may need system administrator privileges to install the update.

4. Restart CORE Generator. During start-up, CORE Generator automatically detects that a new IP has been added to your installation. It allows you to specify which IP customizers ("cores") will be visible in your currently active CORE Generator project. For your current project, you can select the following:

- Display only the latest versions for "All" cores in the catalog.

- Update the catalog view to only add "New" cores to the display.

- Make a "Custom" selection of cores visible in the CORE Generator catalog display for your current project.

5. Determine whether the installation was successful by verifying that the new cores are visible in the CORE Generator GUI.

Acrobat Reader Requirement

Acrobat Reader Version 5 or later must be installed to view core data sheets. You can download the latest Acrobat software from the following Adobe site:


To search for available IP cores, please see:


If you have comments, questions, or problems, please contact Xilinx Technical and Applications Support: http://www.xilinx.com/support/techsup/tappinfo.htm

Known Issues for FIFO Generator v1.0

- On page 2 of the FIFO Generator GUI, the Programmable Empty Type calculation is incorrect for "1_From_Empty" and "2_From_Empty" selections. (Xilinx Answer 19348)

- When customizing the GUI, unable to edit some of the fields, such as component name, input data width, count data width.

(Xilinx Answer 19367)

- FIFO Generator GUI does not show the graphical symbol as mentioned in the data sheet. (Xilinx Answer 19368 )

- When I generate a FIFO Generator core on PC or Linux, an XST synthesis warning and error occur. (Xilinx Answer 19351).

- During Verilog gate-level or timing simulation of a FIFO Generator core, the following error occurs:

"Error: /Xilinx/verilog/src/simprims/X_FF.v(43): $recovery( negedge SET:693111881 ps, posedge CLK &&& (set_clk_enable == 1):693112014 ps, 768 ps ); FAIL_TIME: 693112014ps"

(Xilinx Answer 19352)
AR# 19347
Date 07/28/2010
Status Archive
Type General Article
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