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AR# 19366

6.2 System Generator for DSP - Release Notes and Known Issues List


General Description: 

What are the known issues for System Generator v6.2?


Support Software Issues 


1. What software do I need to install System Generator for DSP? Please see (Xilinx Answer 17966)


2. Why do I get an extra cycle of latency in my design when I use Synplify 7.2.2? Please see (Xilinx Answer 16934)


3. Global clock buffers not instantiated when using Synplify 7.3. Please see (Xilinx Answer 18648)


4. Why do I get simulation mismatches when I use the retiming option for the Delay Block and Synplify 7.3.4? Please see (Xilinx Answer 18643)


5. XST bus elaboration might cause interface changes. Please see (Xilinx Answer 18650)


6. QAM16 demo fails to compile when using Leonardo Spectrum. Please see (Xilinx Answer 19503)


Xilinx Block Set Issues 


1. The CIC filter exhibits overflow for inputs that use the complete dynamic bit range of the data input. To work around this problem, do not use the full dynamic range of your input. Please see (Xilinx Answer 12480)


2. PicoBlaze fails to compile when using the Leonardo synthesis tool. Please see (Xilinx Answer 16923)


3. PicoBlaze compiler script fails when using long module names. Please see (Xilinx Answer 16924)


4. PicoBlaze simulation mismatch for the first clock cycle of an arithmetic or logical instruction. Please see (Xilinx Answer 19499)


5. There are simulation mismatches for the FFTx when the VOUT is low. Please see (Xilinx Answer 18645)


6. Missing clock/clock enable pair when importing HDL as a blackbox. Please see (Xilinx Answer 19500)


7. Verilog `include files are not supported when importing Verilog HDL as a blackbox. Please see (Xilinx Answer 19502)


8. Hardware in the Loop co-simulation block fails to generate if you have only one port in or out of a subsystem. Please see (Xilinx Answer 19504)


9. Simulation mismatched for the reloadable DA FIR, when doing back annotated simulation. Please see (Xilinx Answer 19505)


General Issues 


1. The following error is reported during generation: "Undefined function or variable." Please see (Xilinx Answer 15190)


2. Documentation for older versions of System Generator for DSP are not available after install. Please see (Xilinx Answer 18642)


3. Generation fails when simulation stop function is defined for a model. Please see (Xilinx Answer 18623)


4. User Hardware Co-Sim files disappear when installing System Generator for DSP update. Please see (Xilinx Answer 18646)


5. There is no system-level reset signal available for System Generator for DSP designs. Please see (Xilinx Answer 19498)


6. JTAG Hardware Co-Sim with non Xilinx parts in the chain causes error. Please see (Xilinx Answer 19599).

AR# 19366
Date 05/16/2014
Status Archive
Type General Article