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AR# 19371

MicroBlaze Caches - How do I calculate the tag address size for the instruction and data caches?

Description

General Description: 

How do I calculate the MicroBlaze MHS parameter C_ADDR_TAG_BITS for the instruction cache and C_DCACHE_ADDR_TAG for the data cache?

Solution

The following data cache example helps to explain this process: 

 

The data cache size configured in the hardware (MHS file) is 4 KB: 

PARAMETER C_DCACHE_BYTE_SIZE = 4096 

 

Consequently, the cache_size = 4 KB 

 

The cacheable data memory region (configured in the MHS file) size is 16 MB: 

PARAMETER C_DCACHE_BASEADDR = 0x00000000 

PARAMETER C_DCACHE_HIGHADDR = 0x00FFFFFF 

 

Then: 

cache_word_address_size + tag_address_size = (log(base 2) [cacheable_area_size])  

 

In this case, the cacheable_area_size = 16 MB: 

 

Then:  

cache_word_address_size + tag_address_size = 24  

 

In the other case: 

cache_word_address_size = log(base 2) [cache_size] where cache_size = 4 KB 

 

Then: 

cache_word_address_size = 12  

 

Consequently: 

tag_address_size = 24 - 12 = 12

 

This problem is fixed in the latest 6.3 EDK Service Pack, available at: 

http://www.xilinx.com/ise/embedded/edk.htm.
The first service pack containing the fix is EDK 6.3 Service Pack 1.

AR# 19371
Date Created 09/03/2007
Last Updated 05/16/2014
Status Archive
Type General Article