AR# 19389: 6.2i ISE/EDK - Poor integration of embedded proc into ProjNav using Verilog flow results in "Could not find module/primitive 'myproc'"
6.2i ISE/EDK - Poor integration of embedded proc into ProjNav using Verilog flow results in "Could not find module/primitive 'myproc'"
Keywords: ISE, Project Navigator, XST, embedded, processor, module, primitive, Verilog
General Description: Adding an embedded processor (myproc) into an ISE project (using Project -> New Source -> Embedded Processor) results in the following error when synthesizing the top level file instantiating the processor system:
"ERROR:HDLCompilers:87 - top.v line 6 Could not find module/primitive 'myproc' ERROR: XST failed Process "Synthesize" did not complete."
This error occurs only when the top level file is Verilog. In the VHDL flow, the myproc is seen as a black box and XST fetches the "myproc.ngc" and other netlist files. However, for the Verilog flow, XST fails to look for "myproc.ngc" file. Adding a synthesis attribute for the processor system does not fix the issue.