AR# 19402: 6.2i UniSim - Why are there no longer any unit (intrinsic) delays in the UniSim library components?
6.2i UniSim - Why are there no longer any unit (intrinsic) delays in the UniSim library components?
Keywords: simulation, 100 ps, change, 6.1i
General Description: Why do the UniSim libraries no longer have the 100 ps of unit delays on them?
The intrinsic delay of 100 ps was not a true representation of a behavioral model because a true behavioral model should not have any delays from the input to the output. This change provided the following advantages: - Faster simulation times because there are no longer 100 ps delays to outputs. - Fixed certain race condition occurrences that were caused by the intrinsic delays. - Much easier to debug because when the signal changes at the input to a component, the output reflects this change; no longer need to take the extra 100 ps into consideration.
NOTE: These changes only apply to the non-synchronous elements. The synchronous elements have 100 ps of clock-to-out in the ISE 6.2i libraries and above.