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AR# 19461

ModelSim Xilinx Edition (MXE) - "# ** Error: <filename>.vhd : Subprogram "to_stdlogicvector" is ambiguous"

Description

Keywords: resolving, function, call, stdlogicvector()

When I attempt to compile a file in ModelSim, the following errors occur:

"# ** Error: <filename>.vhd(138): Subprogram "to_stdlogicvector" is ambiguous.
# ** Error: <filename>.vhd(138): Type error resolving function call: to_stdlogicvector.
# ** Error: <filename>.vhd(197): Subprogram "to_stdlogicvector" is ambiguous.
# ** Error: <filename>.vhd(197): Type error resolving function call: to_stdlogicvector.
# ** Error: <filename>.vhd(218): VHDL Compiler exiting"

What do these errors mean, and how can I avoid them?

Solution

VHDL 93 is an extension and modification to the VHDL 87 standard. In this modification, the to_stdlogicvector( )function was updated. Since the function is defined in each of the standards, the ModelSim parser has trouble distinguishing which version to use. To work around this problem, use the -87 switch to explicitly state which version to use. In ModelSim, use one of the following methods to use this switch:

- In the Compile menu, select Compile Options. Un-check "use 1993 Language syntax".
- Alternatively, you can use the switch on the command line as follows:

vcom -87 -explicit -f ping.files
AR# 19461
Date Created 09/03/2007
Last Updated 10/16/2008
Status Archive
Type General Article