AR# 19480

|

6.2 System Generator for DSP - Is it possible to use an asynchronous clock inside the SysGen system?

Description

General Description:

Is it possible to use an asynchronous clock inside the SysGen system?

Solution

For information on this issue, refer to the "Generating Multiple Cycle-True Islands for Distinct Clocks" section in the Xilinx System Generator v6.2 User Guide at:

http://www.xilinx.com/products/software/sysgen/app_docs/user_guide_Chapter_7_Section_2.htm

AR# 19480
Date 12/15/2012
Status Active
Type General Article
People Also Viewed