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AR# 19496

6.3i IP Update 2 CORE Generator - What's New and Known Issues List: IP-DSP

Description

This Answer Record contains "What's New" and "Known Issues" addressed in the 6.3i IP Update 2.

NOTE: IP Update 2 (IP2_G) is bundled with the ISE 6.3i software CD. To access these cores, you must install the ISE 6.3i software; there is not a separate IP Update to install.

Solution

WHAT'S NEW in 6.3i IP UPDATE 2

Convolutional Encoder v4.0

- Support added for Virtex-4.

CORDIC v3.0

- Support added for Virtex-4.

- Improved documentation of quantization error.

Distributed Arithmetic FIR Filter (DA FIR) v9.0

- Support added for Virtex-4.

Direct Digital Synthesizer (DDS) v5.0

- Support added for Virtex-4.

Fast Fourier Transform (xFFT) v3.0

- Support added for Virtex-4.

- New pipelined streaming I/O architecture uses less memory.

- Point sizes extended from 8k to 64k.

Interleaver/De-Interleaver v4.0

- Support added for Virtex-4.

Multiplier Generator v7.0

- Support added for Virtex-4, including XtremeDSP Slice.

Multiply Accumulate FIR Filter (MACC FIR Filter) v5.0

- Support added for Virtex-4.

- Dynamically selectable Coefficient Sets -- allows up to 256 different coefficient sets (already stored in memory) to be dynamically selected.

- Maximum number of channels increased from 32 to 256.

Pipelined Divider v3.0

- Support added for Virtex-4.

- Addition of Clock Enable (CE), Asynchronous Clear (ACLR), and Synchronous Clear (SCLR) inputs (also required for System Generator support).

- Addition of Ready for Data output (RFD).

- Reduced latency compared to V2.0.

- Reduced area compared to V2.0.

Reed Solomon Decoder (RS Decoder) v5.0

- Support added for Virtex-4.

Reed Solomon Encoder (RS Encoder) v5.0

- Support added for Virtex-4.

- Support added for variable number of check symbols.

- Support added for implementation architectures for the check symbol generator.

Sine-Cosine Look-Up Table v5.0

- Support added for Virtex-4.

Viterbi Decoder (Viterbi) v4.0

- Added support for Virtex-4.

- Synchronization feature added.

KNOWN ISSUES in 6.3i IP UPDATE 2

LogiCORE CIC v3.0

- The CIC v3.0 filter exhibits overflow for inputs that use the complete dynamic bit range of the data input.

Please see (Xilinx Answer 12480).

LogiCORE Complex Multiplier v1.0

- Data sheet corrections made.

Please see (Xilinx Answer 19525).

LogiCORE DA FIR Filter

- Simulation mismatch between behavioral and timing simulation occurs when VCS is used.

Please see (Xilinx Answer 19517).

- COREGen memory consumption issues occur with the DA-FIR.

Please see (Xilinx Answer 18663).

- Calculating the clock/pipeline latency of the DA FIR filter.

Please see (Xilinx Answer 4610).

LogiCORE DA FIR Filter (Possibly other cores as well)

- Verilog SimPrim X_SRLC16E reports an error where VHDL SimPrim X_SRLC16E reports only a warning.

Please see (Xilinx Answer 19518).

LogiCORE DA FIR Filter, MAC FIR

- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters.

Please see (Xilinx Answer 5366).

LogiCORE DDC v1.0, MAC FIR v5.0 DA FIR v9.0

- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.

Please see (Xilinx Answer 14202).

LogiCORE DDC v1.0

- DDC can be implemented in the Spartan-3 and Virtex-II Pro devices.

Please see (Xilinx Answer 18937).

LogiCORE 32-pt Configurable FFT v3.0

- The output data appears to be in the wrong bin.

Please see (Xilinx Answer 18901).

LogiCORE 1024-pt FFTv1.0

- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations.

Please see (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0

- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT.

Please see (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0

- The FFT for a Virtex-II device causes PAR warnings and errors.

Please see (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0

- No Verilog model is available for the FFT core.

Please see (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0

- The RESULT signal is not reset properly in the 64-point FFT v2.0.

Please see (Xilinx Answer 15383).

LogiCORE FFT

- Simulation of all fixed netlist FFT (64, 256, 1024) cores generates many warnings.

Please see (Xilinx Answer 14861).

LogiCORE FFT

- Information on output connections to the fixed netlist FFT (64, 256, 1024) cores during a write operation to RAM X (TMS configuration).

Please see (Xilinx Answer 9288).

xFFT v3.0

- Information on Radix 2 or Radix 4 Burst mode output order.

Please see (Xilinx Answer 18825).

LogiCORE MAC FIR v5.0

- Information on support for multiple MAC FIRs with different COE files in the same project.

Please see (Xilinx Answer 16433).

- Back-annotated Verilog simulation causes memory collision errors.

Please see (Xilinx Answer 16106).

- Output registers require extra resources for multi-MAC structures.

Please see (Xilinx Answer 20010).

LogiCORE Multiplier Generator

- A Multiplier Generator Model fails to compile with Synopsys VCS.

Please see (Xilinx Answer 19520).

LogiCORE Reed Solomon v5.0

- Information on the Ghost Enable pin in the GUI.

Please see (Xilinx Answer 19526).

AR# 19496
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article