Why do we no longer have access to a global reset for System Generator for DSP Designs?
In the VHDL, there was a reset signal at the top level, that connected to all the modules. This was removed because it appeared to be a global reset, when in fact it was not. The reason a global reset cannot be implemented is that some of the cores used in System Generator for DSP do not have reset ports; thus, having a single reset port at the top level makes it appear that the entire design is being reset, when there might be cores in the design that cannot be reset.
Here is an example of the VHDL code that is currently generated. This example illustrates that there are lower-level resets that have been terminated with a constant.
In <model>_clock_driver, the connection to "xlclockdriver.vhd" is as follows:
generic map (
period => 1,
use_bufg => false
port map (
sysce => '1',
sysclk => clk_sysgen,
sysclr => '0',
ce => ce_x_0,
clk => clk_x_0
It is recommended that you manually wire up a reset signal to all the synchronous blocks in your design if you want to have a global reset. Starting with 10.1 there is a reset generator block that can be used to generate resets for all the various sample rates in a design. For details, see the Reset Generator help in the System Generator Blockset reference guide.