UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19501

6.3i IP Update 2 CORE Generator - What's New and Known Issues List for IP-System Logic

Description


General Description:

This Answer Record contains "What's New" and "Known Issues" addressed in the 6.3i IP Update 2.



NOTE:

IP Update 2 (IP2_G) is bundled with the ISE 6.3i software CD. To access these Cores, you must install the ISE 6.3i software. There is not a separate IP Update to install.

Solution


WHAT'S NEW in 6.2i IP UPDATE 2



CAM v5.0

-New match logic for improved performance

-Virtex-4 support

-New feature: enhanced ternary mode

-Now supports binary encoded output for depths larger than 256



FIFO Generator v1.1

- Virtex-4 support

- Fixed CR 186725 - XST synthesis exception error. Please see (Xilinx Answer 19531)

- Fixed CR 186949 - Programmable empty type calculation is incorrect for "1_From_Empty" and "2_From_Empty" selections. (Xilinx Answer 19348)



Decoder 8b/10b V6.0

- Added Virtex-4 support



Encoder 8b/10b V5.0

- Added Virtex-4 support



Async FIFO v6.0

- Added Virtex-4 support



Sync FIFO v5.0

- Added Virtex-4 support



DP Block Memory V6.1

- Fixed CR 181031 - Incorrect behavior of output registers in no-change-mode

- Virtex-4 support



SP Block Memory v6.1

- Fixed CR 181031 - Incorrect behavior of output registers in no-change-mode

- Virtex-4 Support



KNOWN ISSUES in 6.2i IP UPDATE 2



FIFO Generator v1.1

- When customizing the GUI, I am unable to edit some of the fields, such as component name, input data width, and count data width. (Xilinx Answer 19367)

- The FIFO Generator GUI does not show the graphical symbol as mentioned in the data sheet. (Xilinx Answer 19368)

- During Verilog gate-level or timing simulation of a FIFO Generator Core, the following error occurs:

"Error: /Xilinx/verilog/src/simprims/X_FF.v(43): $recovery( negedge SET:693111881 ps, posedge CLK &&& (set_clk_enable == 1):693112014 ps, 768 ps ); FAIL_TIME: 693112014ps" (Xilinx Answer 19352)

- I cannot specify the initialization value of DOUT to a value other than "0" when using the asymmetric ports. (Xilinx Answer 19522)



Encoder 8b/10b v5.0

- Simulation mismatches with KERR when I use VCS 7.1R5. Please see (Xilinx Answer 19521).
AR# 19501
Date Created 09/03/2007
Last Updated 07/28/2010
Status Archive
Type General Article