AR# 19507

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6.3 System Generator for DSP - Why do I receive an error message specifying that my non-memory mapped ports cannot be found when doing JTAG Hardware in the Loop Co-Simulation?

Description

General Description: 

Why do I get an error message specifying that my non-memory mapped ports cannot be found when doing JTAG Hardware in the Loop Co-Simulation?

Solution

When creating non-memory mapped ports, ensure you do the following: 

 

1. Create a library and add a gateway. 

2. Name the gateway with the name of your board specific port (this name must match the port name used in the post-generation function and UCF file). 

3. Select the gateway by clicking it. 

4. In the MATLAB command window, type the following: 

>> xlSetNonMemMap(gcb, 'Xilinx', 'jtaghwcosim'); 

5. Save the library. 

 

You can find more information about JTAG Hardware in the Loop Co-Simulation under the Using FPGA Hardware in the Loop of the System Generator for DSP Users Guide. 

 

http://www.xilinx.com/products/software/sysgen/app_docs/user_guide.htm

AR# 19507
Date 05/16/2014
Status Archive
Type General Article
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