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AR# 19525

LogiCORE Complex Multiplier v1.0 - Where can I find corrections to the data sheet for the Complex Multiplier?


Keywords: COREGen, complex, multiplier, 1.0, data sheet, datasheet

Where can I find corrections to the data sheet for the Complex Multiplier?


Page 3. Table 1: SCLR is listed as an input Pin. However, it is called RST on the GUI and when Core is generated.

Page 4. Data Width Paragraph. It is stated that the allowed product Width is 8 to A_WIDTH + B_WIDTH +1.
However, the GUI allows a minimum value of 4 for the product width and it is also stated in Table 3 that the range is 4 to A_WIDTH + B_WIDTH +1.

Page 8: Pipelining the Design Paragraph. It is mentioned in a number of the bullet points that "pipelining greatly reduces the latency".
This should say that adding pipelining increases the latency.

Page 9 of the data sheet contains some information relating to Core Resource Utilization. In the relevant paragraph it states:
"For an accurate measure of the usage of primitive, slice, and CLBs for a particular instance, check the Display Core Viewer after Generation checkbox."
The GUI utilization is always: 0 LUT sites used, 0 registers used.

If you try one of the examples on Page 10, you will see the following:
For example, Table 7. 32x16, Product=32, IN=1, OUT=1, Optimize for Speed. The number of Slices should be 102.
The information panel on the GUI indicates Approximate Slices=1 and the Display Core Viewer indicates 0 LUT sites used, 0 registers used.

Please see (Xilinx Answer 21591) for a detailed list of LogiCORE Complex Multiplier Release Notes and Known Issues.

AR# 19525
Date 03/02/2008
Status Archive
Type General Article