We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19532

ModelSim (MXE, SE, PE) - ModelSim hangs when simulating Verilog module with conditional generate instances


Keywords: MXE, if, VSIM, hang

Urgency: Standard

General Description:
If a UUT has conditional generate instances with one module per conditional branch, the initial ModelSim window will appear but will hang. The modules in each individual conditional generate instance can be simulated with no problem using ModelSim. The problem occurs only when multiple instances are being generated and they are in named conditional blocks.


The MTI 5.7/5.8c tool has a memory leak in the code, and that is why it hangs. The memory leak is due to the named blocks.

To work around this issue, rewrite the generate block in the affected module as follows:

For example:
if(x == 2)
Module1 #(.a(a), .b(b)) c (.d(d),.i(i),.o(o));
else if(x == 3)
Module2 #(.a(a), .b(b)) c (.d(d),.i(i),.o(o));
Module3 #(.a(a), .b(b)) c (.d(d),.i(i),.o(o));

You can also work around this issue, if the module is changed, by not using conditional instance generation; then, the simulation will work correctly.

This will be fixed in the 5.8d version of the software.
AR# 19532
Date 10/17/2006
Status Archive
Type General Article