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AR# 19542

7.1i Timing Analyzer Virtex-4 - Paths through IDELAY are not analyzed

Description

General Description:

The timing report is not reporting any paths through the IDELAY or ILOGIC components of my design.

Solution

This is scheduled to be fixed in the next major release of the design tools.

AR# 19542
Date Created 09/03/2007
Last Updated 01/18/2010
Status Archive
Type General Article