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AR# 19550

6.2i SP3 SimPrim - Memory collision error message on the VHDL RAM block models might be incomplete

Description

Keywords: RAMB16, missing, information, error, message

Urgency: Standard

General Description:
Sometimes when running a VHDL model in simulation, the memory collision error message might not be complete.

The message should be something like this:

"ASSERT/ERROR (time 2150 NS) from procedure :<instance_name> (architecture simprim.X_RAMB16:X_RAMB16_V)
Memory Collision Error on RAMB16_S36_S36: at simulation time 2150 NS.
A read was performed on address 0000 (hex) of port B while a write was requested to the same address on Port A The write will be successful however the read value is unknown until the next CLKB cycle."

At times the message might read as follows:

"ASSERT/ERROR (time 2150 NS) from procedure :<instance_name>(architecture simprim.X_RAMB16:X_RAMB16_V)
Memory Collision Error on RAMB16_S36_S36: at simulation time 2150 NS.
A read was performed on address 0000 (hex)"

That is, the latter part of the message is missing.

Solution

This is a problem with the messaging section of the model, and it will be fixed in the ISE 6.3i release.
AR# 19550
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article