The Spartan-3 FPGA DC and Switching Characteristics Data Sheet does not specify the cycle-to-cycle output jitter. (Previous Spartan-II/-IIE data books included this specification for the DLL.)
What is the cycle-to-cycle output jitter for DCM?
Part of the cycle-to-cycle jitter comes from the DCM_TAP parameter, which is described in the Spartan-3 FPGA DC and Switching Characteristics Data Sheet at:
However, other factors such as input jitter, internal DCM delay, and routing also contribute to the resulting cycle-to-cycle jitter.
For timing budgeting, use the period jitter. Please see (Xilinx Answer 13645) for more information.
For a description of cycle-to-cycle jitter, please see (Xilinx Answer 12010).