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AR# 19567

Spartan-3, DCM - What is the cycle-to-cycle output jitter for DCM?

Description

The Spartan-3 FPGA DC and Switching Characteristics Data Sheet does not specify the cycle-to-cycle output jitter. (Previous Spartan-II/-IIE data books included this specification for the DLL.)

What is the cycle-to-cycle output jitter for DCM?

Solution

Part of the cycle-to-cycle jitter comes from the DCM_TAP parameter, which is described in the Spartan-3 FPGA DC and Switching Characteristics Data Sheet at:

http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf

However, other factors such as input jitter, internal DCM delay, and routing also contribute to the resulting cycle-to-cycle jitter.

For timing budgeting, use the period jitter. Please see (Xilinx Answer 13645) for more information.

For a description of cycle-to-cycle jitter, please see (Xilinx Answer 12010).

AR# 19567
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article