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AR# 19570

7.1i XST - MAP: "ERROR:LIT - ADDRA/B[14] should not tied to GND for Virtex-4 block RAMS in non-cascading mode."

Description

Keywords: cascade, VCC

When I instantiate block RAM primitives in a Virtex-4 part, and the upper address bit is left unconnected, XST grounds the unused bit and the following MAP error occurs:

"ERROR:LIT - Pin ADDRA14 of a RAMB16 block should be left dangling or tied to VCC
in non-cascading mode. Instance RAMB16_INST (of type RAMB16) either is not
using CASCADEINA/CASCADEOUTA pins or has the property RAM_EXTENSION_A set to
NONE."

Solution

To work around this issue, tie the unused bit to "1" in your Verilog or VHDL code. You can tie the unused bit during instantiation, or you can tie it to a signal that is tied to a logic "1" value.

This issue is fixed in ISE 8.1i.
AR# 19570
Date Created 09/03/2007
Last Updated 01/07/2009
Status Archive
Type General Article