We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 1964

XNF specification - Naming Conventions for nets, buses, components and pins


Keywords: naming, convention, XNF, specification, nets, buses, component, pins, labels

Urgency: Standard

General Description:
A specific naming convention must be followed when nets, buses, components, and pins are named in a design in order to follow the XNF specification. While this list covers most of them, please refer to the user guide for your design entry tool for additional conventions that may apply specifically to the design entry tool/simulator that you are using.


FPGA names for nets, buses, components, and pins must follow these conventions:

- Only A-Z, a-z, 0-9, _, and - are allowed in user-defined names. No other characters should be included in names.

- No spaces are allowed.

- Names must contain at least one non-numeric character.

- Names cannot be more than 1024 characters long.

- Do not use reserved words such as:
CLB, IOB, CCLK, DP, GND, VCC, RT, PWRDN, RST, TDO, BSCAN, M0, M1, M2, STARTUP, as well as package pin names (P1, P2, A4, B5, etc.), CLB names (AA, AB, R1C3, etc) or Xilinx primitive names (FD, PULLUP, BUF, etc).

- Square brackets, [], are generally used for bus notation and should not be used unless defining the bounds of a bus.
AR# 1964
Date 03/03/2003
Status Archive
Type ??????