The Digital Down Converter (DDC) Core produces no output for small decimation numbers when simulating a programmable CIC implementation of the core.
This is a known issue with the programmable decimation implementation of the core. When the CIC is set to have a programmable decimation, the size of the output bit width becomes large to accommodate the worst-case scenario, which is for very large decimations. This very large output bit width must be truncated and the current implementation of the core selects the MSBs of the output and the width is defined by you in the GUI.
However, for lower decimation rates the output bit width of the CIC is far smaller and, consequently, the MSB truncation removes all of the useful data from the data path and nothing is seen in the simulation output.
The solution to this problem is to implement a circuit that can variably select the output bits of the CIC based on the programmable decimation rate specified by you.
You can build the DDC from the scratch output of other IP cores available from the CORE Generator. The cores required are the DDS, CIC, Multiplier, DA FIR and/or MAC FIR; extra circuitry is required for rounding and quantization.
The best development environment for building and testing this function is the System Generator for DSP. There are some example designs provided with the System Generator that you can use as a starting point for building your own DDC. Refer to the System Generator documentation for more information on accessing the demos and example designs. For more information on the System Generator, see: