How do I make the Done pin stay Low after configuration so I can load my user application data from the PROM into the FPGA for processor use?
To keep Done Low, set DONE_Cycle:Keep when generating the bit file with BitGen. This setting will keep DONE low even after successful configuration.
Other cautions should also be taken if Done is set to Keep.
- CCLK should be wired to user I/O so that you can drive the CCLK to clock the data out of the PROM.
- The BitGen Persist option should not be used as SelectMap pins must be used as user I/Os in order to retrieve data from PROM. You are responsible for developing IP to read data from PROM.