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AR# 19699

Virtex-II Pro, Virtex-II ProX, Virtex-4 FX RocketIO - Board Debug Steps


Here are some questions that can be asked when you run into a problem with an MGT in Virtex-II Pro. These are questions that are useful when running through the debug process. Everything here is good information to have when calling the hotline or information to obtain when you are debugging.



What is the application?

What speed are you transmitting at?

What is the serial speed? What is the parallel speed?

What is the failure? Where did the failure/error occur?

Did this happen on the RX/TX? What signals are indicating this error/failure? Give as much description as possible.

What are the locations of the failing MGTs?

Where on the device are the MGTs located? What are the device details?

a. Device

b. Package

c. Speed Grade

d. Temperature Grade

e. Revision/Date Code

f. Lot Code

Is this device on a Xilinx board or a custom board? If Xilinx, which one?

What is the fabric interface?

What is the width of the data entering your fabric? If the data path is 2- or 4-byte wide and if you see RXCOMMADET toggle, but data is incorrect, check if COMMA_ALIGN_MSB=FALSE or ALIGN_COMMA_WORD is set correctly. If so, it might be that the comma is being aligned in the LSB and so the byte alignment might be off. For the 4-byte wide datapath, there is some additional logic that is required in the fabric, referenced on Pg. 92 of the User Guide. What speed is the data being clocked into the fabric?

Is Xilinx IP being used?


What are the Encoding / Decoding Details?

a. 8B/10B

i. Internal

ii. External

b. 64B66B

c. Custom

Max 0 or 1 run length of serial data if not using 8B/10B

What are the REFCLK details?

a. Manufacturer

b. Clock source (Oscillator, Frequency Synthesizer etc.)

c. Jitter spec and measurement

MGT Power Supply Details

a. Supply Type (Switching or Linear)?

b. Filtering Details

c. External\Internal Filtering Caps

d. Capacitors - which ones?

Jitter Information (Dj/Rj/Tj) (if measured or spec'd, specify which it is)

a. Clock

b. Tx Side

c. Rx Side

What are the MGT component details?

a. Baud Rate

b. Channel Bonding Info

c. Pre-Emphasis

d. Voltage Swing

e. Full-Rate\half Rate Mode

Does it work in loopback mode?

Parallel or Serial or both? If it does not work in serial loopback and works in parallel loopback, it might be that the termination is mismatched or not done properly.

Does it work at lower data rates?


What is the Signal Topology?

a. Is this Chip-to-Chip?

b. Is this Backplane?

c. Is this in a Point-to-point, loop or mesh configuration?

d. What is the PCB Material?

e. What are the trace geometries?

f. Vias, # & Type of Connectors?

g. (Attach additional details on board stackup, connector layout, etc., if possible)

What are your Select IO Interfaces?

a. Total I/O Used

b. I/O Standards and corresponding VCCO voltages

c. Switching frequencies

d. Slew Rates

e. Interface Types (e.g., PCI)

What is the device at far end?

a. Interoperability Details

b. Is the link AC/DC coupled?

What is the Link Protocol?

a. What is the Industry Standard?

b. Is this a Proprietary Link?

Was WASSO Analysis done?

If so, what were the results?

a. Time domain measurement

b. Measure each MGT supply before and after ferrite bead relative to MGT GNDA pin

c. Must be real-time scope (not sampling scope) with > 2.5 GS/s sampling rate

Output in ".CSV" format preferred

Cable Details (if any in path)

a. Type

b. Length

Has the customer done any signal Integrity Analysis?

If so, include details.

AR# 19699
Date 12/15/2012
Status Active
Type General Article
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