We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19763

v2.1 COREGen Aurora - For 4-lane module, XST quits with error "ERROR: cmain.c 3082:"


Urgency: Medium 


General Description: 

Single 4-byte lane modules do not synthesize with XST. XST quits with an internal error: 


"ERROR: cmain.c 3082:"  


Multi-lane modules are not affected. This module synthesizes in Synplify.


When the wires are concatenated, XST converts them back to their original bus form with no change. 


To resolve this, change the following lines in bold italics in Aurora Lane Instantiation Code in the top level file from: 


// RX_LL Interface 

.RX_PAD({rx_pad_i[0], rx_pad_i[1]}), 

.RX_PE_DATA({rx_pe_data_i[0:15], rx_pe_data_i[16:31]}), 

.RX_PE_DATA_V({rx_pe_data_v_i[0], rx_pe_data_v_i[1]}), 

.RX_SCP({rx_scp_i[0], rx_scp_i[1]}), 

.RX_ECP({rx_ecp_i[0], rx_ecp_i[1]}), 


to the following in italics 


// RX_LL Interface 






AR# 19763
Date 05/16/2014
Status Archive
Type General Article
Page Bookmarked