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A new BitGen option has been introduced to improve Spartan-3 block RAM timing. Do I need to regenerate my bitstream?
New BitGen settings have been introduced for the Spartan-3 family to improve Block RAM timing. Block RAM timing is controlled by settings in the configuration bitstream, and optimal bitstream settings were identified to improve Block RAM timing. These settings affect the Block RAM control logic and improve the timing margin available for Block RAM write operation, which consequently improves yield. The improvement to the Block Ram timing will have no affect on existing customer designs because older silicon still meets the current Block Ram timing specifications.
Silicon testing after September 13, 2004 will use the new BitGen settings. Consequently, you must use these new settings for your design to meet the guaranteed Block RAM timing specifications. It is important that you use the latest software when targeting the latest silicon. This will not be a problem if you are using ISE 6.3i Service Pack 1, because starting with this version, the Xilinx bitstream generator (BitGen) generates the new settings automatically. If you use an ISE version older then 6.3.01i and you generate a bitstream, you can make sure that your design incorporates these new settings by manually setting these special BitGen options. For information on how to set these options, see "Creating New Settings using ISE software prior to 6.3.01i" below. Incorporating these setting into your bitstream will enable you to use the bitstream with newer silicon (date code of 0433 or later). Using the updated bitstream on older silicon will have no adverse affects since the older silicon already meets current Block RAM timing specifications.
These settings apply to all Spartan-3 FPGAs except the XC3S200 and the XCS400, which are already in production and do not require any bitstream changes. Designs using the XC3S50, XC3S1000, XC3S1500, XC3S2000, XC3S4000, or XC3S5000 must use the latest bitstream settings generated by ISE 6.2.01i or later. If using software older than 6.3.01i, you must regenerate the bitstream with the new settings, see "Creating New Settings using ISE software prior to 6.3.01i" below. The settings are not required for the XC3S200 and XC3S400 FPGAs, but there are no adverse affects if the new bitstream settings are accidentally applied to the XC3S200 or XC3S400.
Creating New Settings using ISE software prior to 6.3.01i
If using software prior to 6.3i, Service Pack 1, you can still create correct bitstreams using existing ISE software. However, all the Block RAMs in the FPGA must be in either the WRITE_FIRST or the NO_CHANGE mode. The following method does not apply if any of the Block RAMs are in READ_FIRST mode. Fortunately, the WRITE_FIRST mode is the default mode, and most Block RAM configurations are in WRITE_FIRST mode. The BitGen settings shown below will overwrite the default values generated by the Xilinx ISE software.
If you are using the READ_FIRST mode and need to generate a new bitstream before Service Pack 1, open a WebCase at: