In summary, the Digital Clock Manager (DCM) status pins for Spartan-3 represent the following:
The DCM status pins for Spartan-3E/-3A represent the following:
Status<1>: After the clock is lost, there is a several cycle latency before the Status<1> pin goes High. This occurs within 1-8 CLKIN clock cycles if any single rising edge of CLKIN does not arrive at the expected time (within a +/- one half clock cycle window).
After another rising edge arrives, the "DLL CLKIN Stopped" (Status<1>) signal goes Low again within 1-4 CLKIN clock cycles. The cycle latency depends upon frequency, with the higher frequency clocks leading to greater latency. The DCM resumes functionality when the clock resumes.
The DCM might lose the LOCKED signal if the CLKIN is stopped for a short period. Consequently, you should monitor LOCK and the Status<1> bit to determine if the output clock is valid. If DCM loses the LOCKED signal, you must reset the DCM for it to resume functionality. For more information, see the Spartan-3 Generation FPGA User Guide.
If the DCM has locked to the input clock signal, it is possible to momentarily stop the CLKIN input clock with little impact to the deskew circuit, provided that these guidelines are followed:
Status<2>: If you are using the CLKFX or CLKFX180 outputs, and the wrong CLKIN cycle is skipped (or if CLKIN stops altogether), the CLKFX/FX180 outputs freeze, and will not recover without a reset. The "CLKFX Stopped" status signal has been added so that this situation is easier to recognize. After it asserts, it will not de-assert until the DCM is reset.
For more information on the Spartan-3, Spartan-3E, and Spartan-3A DCM status pins, see the Spartan-3 Generation FPGA User Guide.