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AR# 19851

6.3i NetGen, Timing Simulation - Running a timing simulation causes "Input Error : RST on instance <instance_name> must be asserted for 3 CLKIN clock cycles."

Description

Keywords: NetGen, timing, simulation, ERROR, error, Virtex-4, DCM, RST, 3, clock

Urgency: Standard

General Description:
When I running a timing simulation, the following error appears, even when Reset has been asserted for more than three clock cycles:

"# Input Error : RST on instance <instance_name> must be asserted for 3 CLKIN clock cycles."

This also causes the DCM not to lock.

Solution

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19851
Date Created 09/03/2007
Last Updated 11/10/2008
Status Archive
Type General Article