UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19855

6.3i SimPrim - TXRUNDISP goes to X when a timing simulation is performed with the GT10 model

Description

Keywords: SimPrim, VHDL, timing, simulation, ModelSim, NC-VHDL, TXRUNDISP, X_GT10, Rocket-IO

Urgency: Standard

General Description:
When a timing simulation is performed, the following discrepancies between UniSim- and SimPrim-based models occur:

1. TXRUNDISP goes to X after some time.
2. RXDISPERR and RXNOTINTABLE go to X after TXOUTCLK starts.
3. PMARXLOCK goes High-Low very frequently.

Solution

This problem has been fixed in the latest 6.3i Service Pack available at:
http://support.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 6.3i Service Pack 1.
AR# 19855
Date Created 09/03/2007
Last Updated 11/18/2008
Status Archive
Type General Article