Description

General Description:

How do I set the different I/O standards for Virtex using the xc_padtype attribute?

This is a Virtex-only attribute that specifies an I/O buffer standard. For example, applying AGP to an IBUF results in the use of an IBUF_AGP instead of an IBUF primitive.

Values of I/O Standards:

AGP, CTT, F_2, F_4, F_6, F_8, F_12, F_16, F_24, GTL, GTLP, HSTL_I,

HSTL_III, HSTL_IV, LVCMOS2, PCI33_3, PCI33_5, PCI66_3, S_2, S_4,

S_6, S_8, S_12, S_16, S_24, SSTL2_I, SSTL2_II, SSTL3_I, SSTL3_II

Please reference (Xilinx XAPP133): "Using the Virtex SelectI/O Resource" for more information on using Xilinx I/O standards. For information on passing I/O standards through generics/parameters, please see (Xilinx Answer 17291).

Solution

SDC

define_attribute <port> xc_padtype "<i/o_standard>"

Verilog

module test_padtype (a, b, clk, rst, en, bidir, q);

input [3:0] a /* synthesis xc_padtype = "IBUF_AGP" */;

input [3:0] b;

input clk, rst, en;

inout [3:0] bidir /* synthesis xc_padtype = "IOBUF_CTT" */;

output [3:0] q /* synthesis xc_padtype = "OBUF_F_12" */;

VHDL

library ieee, synplify;

use ieee.std_logic_1164.all;

use synplify.attributes.all;

entity test_padtype is

port( a : in std_logic_vector(3 downto 0);

b : in std_logic_vector(3 downto 0);

clk, rst, en : in std_logic;

bidir : inout std_logic_vector(3 downto 0);

q : out std_logic_vector(3 downto 0));

attribute xc_padtype of a : signal is "IBUF_SSTL3_I";

attribute xc_padtype of bidir : signal is "IOBUF_HSTL_III";

attribute xc_padtype of q : signal is "OBUF_S_8";

end entity;