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AR# 19959

6.3i Install - ISE Service Pack 3 Release Notes/README


Keywords: SP1, SP2, Solaris, UNIX, PC, Linux, software, update, Web update

This README Answer Record contains the Release Notes for 6.3i Service Packs. The Release Notes include installation instructions and a list of the issues that are fixed by 6.3i Service Packs. Note that ISE Service Packs are cumulative; consequently, fixes found in Service Pack 1 are also found in Service Packs 2 and 3.


A successful installation of Xilinx ISE 6.3i Service Pack 3 updates your software version number to 6.3.03i.

1. The destination directory specified during the set-up operation must contain an existing Xilinx ISE installation. Only existing files are updated. Any new device support not previously installed should first be installed from the Xilinx ISE CD before adding the Service Pack.
2. You must set the XILINX environment variable before installing the Service Pack.

Installation Instructions for PC Users

Use one of the following methods:

Method 1
1. Download "6_3_03i_pc.exe" from:
2. Run "6_3_03i_pc.exe".

Method 2
1. Establish a working Internet connection using Internet Explorer.
2. Use the WebUpdate program using one of the following methods:
- Run Start -> Programs -> ISE6 -> Accessories -> WebUpdate.
- Run "Software Updates..." (under the Help menu in Project Navigator).

Installation Instructions for Solaris Users

1. Download "6_3_03i_sol.tar.gz" from:

2. Unzip and untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
tar xvzf 6_3_03i_sol.tar.gz

3. Run "6_3_03i_sol/setup".

Installation instructions for Linux Users

1. Download "6_3_03i_lin.tar.gz" from:

2. Untar the downloaded file into an empty "staging" directory.

For example:
cd /home/staging_dir
tar xzvf 6_3_03i_lin.tar.gz

3. Run "6_3_03i_lin/setup".

Issues Fixed by 6.3i Service Packs

Architecture Wizard

(SP1) 6.3i Architecture Wizard - Incorrect HDL generated for DCM/PMCD when DCM CLKDV clock is connected to PMCD CLKA (Xilinx Answer 19945)


(SP3) 6.3i SP3 BitGen- BitGen has been updated to fix several incorrect error and configuration settings for Virtex-4. Please update BitGen for Virtex-4 configuration (Xilinx Answer 20394)
(SP3) 6.3i SP3 BitGen - BitGen has been updated to correctly set IOB attributes for Virtex-II Pro SSTL IO standards (Xilinx Answer 20395)
(SP3) 6.3i SP3 BitGen - BitGen errors out with "DesignRules:462 - Chipcheck : Incompatible IO standard..." while the two reported IO standards are exactly the same (Xilinx Answer 20397)
(SP2) 6.3i BitGen - Virtex-4 allows you to change the default pull-up resistor on dedicated configuration pins, but this does not seem to be supported by the software (Xilinx Answer 20131)
(SP2) 6.3i BitGen - Virtex-4 VREF does not function correctly (Xilinx Answer 20132)
(SP2) 6.3i BitGen - Non-dedicated System Monitor input pins do not function correctly, resulting in System Monitor not receiving any input (Xilinx Answer 20133)
(SP2) 6.3i BitGen/iMPACT - Virtex-4 verify operation fails with "ERROR:iMPACT:396 - readback to map unsuccessful" (Xilinx Answer 20134)
(SP2) 6.1i BitGen - Virtex-II Pro (V2P20) DCI IOBs fail to function correctly when DCI UpdateMode is set to Quiet or Continuous (Xilinx Answer 20135)
(SP2) BitGen - Why is there an option to set the configuration rate to 100 MHz for Spartan-3? (Xilinx Answer 20080)
(SP2) 6.3i BitGen - Virtex-4 MGT might not function as expected (Xilinx Answer 20136)
(SP2) 6.3i BitGen - Virtex-4 PPC and EMAC initialization is incorrect (Xilinx Answer 20137)
(SP2) 6.3 BitGen - "ERROR:DesignRules:326 - Blockcheck: Dangling PPC405_ADV input" (Xilinx Answer 19968)
(SP2) 6.3i BitGen - Virtex-4 design errors out with "ERROR:DesignRules:330 - Blockcheck: Dangling RSTINV input" (Xilinx Answer 20138)
(SP2) 6.3i BitGen - Virtex-4 designs containing RSDS_25 IO standards fail at BitGen with "ERROR:DesignRules:698" (Xilinx Answer 20139)
(SP1) Virtex-II Pro - Four new I/O standards are available with a differential termination at the differential input pair (Xilinx Answer 17244)
(SP1) Spartan-3 - BitGen setting to improve Spartan-3 block RAM timing (-g Ibram_wdel0:1) (Xilinx Answer 19825)


(SP1) 6.2i BSDLAnno - Syntax Error on post-configuration BSDLs (Xilinx Answer 19898)
(SP1) 6.2i BSDLAnno 6.2.03i : XC2C128 BOUNDARY_REGISTERs all declared as INPUT (Xilinx Answer 19899)


(SP1) 6.3i CompXLib - When I compile for VCSi, an error reports "Error-[URMI] Instances with unresolved modules remain in the design." (Xilinx Answer 19847)
(SP1) 6.3i CompXLib - When compiling for VCS, I do not receive a message if the compilation fails due to a license check out problem (Xilinx Answer 19848)

Constraints Editor

(SP2) 6.2i Constraints Editor - Nets appear in clock list that are not clocks (Xilinx Answer 19603)
(SP1) 6.3i Constraints Editor - GT11/EMAC design, not all clocks listed (Xilinx Answer 19949)


(SP2) 6.3i CPLDFit CoolRunner-II - Output permanently set to 'Z' (high impedance, 3-state) fails to function in device (Xilinx Answer 19830)
(SP1) 6.3i CoolRunner-II Hprep6 - "Warning: CPLD:814 - Programming output (JEDEC) for device type XC2Cxxxx is not supported in this release" (Xilinx Answer 12104)


(SP3) 6.3i Data2MEM - Data2MEM will generate incorrect BIT files for Virtex-4 devices (Xilinx Answer 20425)
(SP2) 6.3i Data2MEM - iMPACT - Error shows in the status register, CRC Error bit is NOT 0 for Virtex-4 devices (Xilinx Answer 19967)


(SP2) 6.3i Virtex-4 DRC - "ERROR:DesignRules:326 - Blockcheck: Dangling DSP48 input" (Xilinx Answer 20160)
(SP2) 6.3i Virtex-4 DRC - DRC does not flag all improper IOB to DCM connections (Xilinx Answer 20161)


(SP2) 6.2i ECS - "ERROR:HDLParsers:816 - <file_name>.vhf Line <##>. Attribute KEEP. Two specifications for entity <inst_name>" (Xilinx Answer 20148)


(SP3) 6.2i iMPACT - Generating an ACE file for the XCV2P2 device results in "ERROR:iMPACT:1559 - No devices on the chain. Cannot created SVF file "c:\...\rev0\rev0.svf" (Xilinx Answer 20144)
(SP3) 6.2i SP3 iMPACT - iMPACT reports error: "The dynamic link library MSVCP60.dll could not be found in the specified path..." (Xilinx Answer 19844)
(SP2) 6.3i iMPACT - Configuration with the SVF or ACE file running at high TCK speed might result in configuration failure (Xilinx Answer 20140)
(SP2) 6.2i iMPACT - Programming NKY key to 2v1000 in SVF mode works only when done twice; otherwise, encrypted bitstream configuration fails (Xilinx Answer 20141)
(SP2) 6.3i iMPACT - Platform Flash (XCFxxP) PROM does not store customer code after power is toggled (Xilinx Answer 20142)
(SP1) 6.1i SP3 iMPACT/PROMGEN - Unable to generate compressed PROM file for the Platform Flash PROMs (XCFxxP) (Xilinx Answer 19904)
(SP1) 6.3i iMPACT - Configuration with Virtex-II Pro encrypted bitstream fails; Done does not go High (Xilinx Answer 19901)
(SP1) 6.2i SP3 iMPACT - Verify fails with mismatches, but iMPACT GUI reports success (Xilinx Answer 19902)
(SP1) 6.2i SP3 iMPACT - iMPACT errors out with "Error:Portability:90" and "Error:iMPACT:514" when erasing XCF32P with MultiPRO (Xilinx Answer 19903)


(SP3) 6.3i Virtex-4 MAP - "ERROR:LIT - The attribute ALMOST_FULL_OFFSET and/or ALMOST_EMPTY_OFFSET setting for instance fifo16_rd_fall (of type FIFO16) is not valid." (Xilinx Answer 20020)
(SP3) 6.3i Virtex-4 MAP - Unused carry logic is not being trimmed (Xilinx Answer 20444)
(SP3) 6.3i Virtex-4 MAP - Cascaded DSP48s have unroutable pins because ".CEC" pin is incorrectly tied off (Xilinx Answer 20445)
(SP3) 6.3i Virtex-II PAR - "ERROR:Place:379 - Unable to place the following group for unknown reason" (Xilinx Answer 20446)
(SP3) 6.3i Virtex-4 MAP - IOBDELAY=NONE ignored on input nets of bidirectional pad (Xilinx Answer 20450)
(SP2) 6.3i Virtex-II MAP - Flip-flop (FF) driven by COUT not packed to make use of CIN resource (Xilinx Answer 20162)
(SP2) 6.3i Virtex-II PRO MAP - Incorrect sizing of RPM GRID macro leads to pack error (Xilinx Answer 20163)
(SP2) 6.3i Virtex-4 MAP - Packer creates unroutable connection by pushing flip-flop (FF) with two loads into an OLOGIC component (Xilinx Answer 20164)
(SP2) 6.3i Virtex-4 MAP - MAP hangs during the "running cover" phase on a Virtex-4 design (Xilinx Answer 20165)
(SP2) 6.3i Virtex-4 MAP - "ERROR:LIT - Pin ADDRA14 of a RAMB16 block should be left dangling or tied to VCC in non-cascading mode..." (Xilinx Answer 20170)
(SP2) 6.3i Virtex-4 MAP - IDELAYCTRL components are incorrectly trimmed if RDY pin is left dangling (Xilinx Answer 20171)
(SP2) 6.3i Virtex-4 MAP - BYPASS property is lost unless the IOSTANDARD property is on PAD (Xilinx Answer 20173)
(SP2) 6.3i Virtex-4 MAP - "FATAL_ERROR:Ncd:basnccomp.c:3589: - Cannot find other bel for unconnected pin on bel BEL_XLXI_1.PMCD:REL ..." (Xilinx Answer 20176)
(SP1) 6.3i Virtex-II MAP - LUT not placed in same slice as carry chain for counter MSB (Xilinx Answer 19908)
(SP1) 6.3i Virtex-4 MAP/PAR - "ERROR:Place:181 for design with SSTL2_II_T_DCI/SSTL18_II_T_DCI" (Xilinx Answer 19909)
(SP1) 6.3i Virtex-4/Spartan-3 MAP - "Error:Pack:313..." is issued when valid LOC and Area Group constraints are combined (Xilinx Answer 19910)
(SP1) 6.3i Virtex-4 MAP - Incorrect check of CLKFB of DCM driven from CLK2X via PMCD and BUFG (Xilinx Answer 19911)
(SP1) 6.3i Virtex-4 MAP - Support for the IOSTANDARD RSDS_25 has been added (Xilinx Answer 19912)
(SP1) 6.3i Virtex-II MAP - Timing driven packing is not working correctly with Guide Mode (Xilinx Answer 19913)
(SP1) 6.3i Virtex-4 MAP - Local clocks not promoted to BUFRs as expected (Xilinx Answer 19914)
(SP1) 6.3i Virtex-4 MAP - "FATAL_ERROR:MapLib:whtmmfddr_retarget.c:713:" (Xilinx Answer 19115)
(SP1) 6.3i Virtex-4 MAP - Packer fix for pad bypass feature is needed for PCI cores (Xilinx Answer 19918)
(SP1) 6.3i Virtex-4 MAP - DRC for TQ pin of OSERDES errors out on valid case (Xilinx Answer 19919)
(SP1) 6.3i Virtex-4 MAP - "FATAL_ERROR:MapLib:basmmpin.c:67:1.16 - set_sig, already have sig" (Xilinx Answer 19920)


(SP1) 6.3i NetGen, Timing Simulation - Running NetGen on a Virtex-4 Monitor/ADC designs causes "ERROR:Anno -KEEP_HIERARCHY was corrupted" (Xilinx Answer 19849)
(SP1) 6.3i NetGen, Timing Simulation - Running a timing simulation causes "Input Error : RST on instance <instance_name> must be asserted for 3 CLKIN clock cycles." (Xilinx Answer 19851)
(SP1) 6.3i NetGen, Timing Simulation - A Virtex-4 PowerPC designs fails, reporting: "ERROR:Anno:207 - 1 block(s) were unexpanded, including the following:" (Xilinx Answer 19852)
(SP1) 6.3i NetGen, Timing Simulation - NetGen is not writing out INIT attributes for ODDR and IDDR if non-default values are used (Xilinx Answer 19728)
(SP1) 6.3i NetGen, Timing Simulation - The SRTYPE value is set as SYNC for ODDR and IDDR, even though it is set as ASYNC in the HDL code (Xilinx Answer 19729)
(SP1) 6.3i NetGen, Timing Simulation - Running a non-behavioral simulation with the Virtex-4 EMAC causes: "Error: <filename>.vhd(<line_no>): Unknown identifier 'rgmii." (Xilinx Answer 19853)
(SP1) 6.3i NetGen, Timing Simulation - Simulator errors regarding incorrect attributes occur on GT11 back-annotated netlists (Xilinx Answer 19723)
(SP1) 6.3i PrimeTime/NetGen - SDF causes PrimeTime annotation issue due to the pulse width check (Xilinx Answer 19955)


(SP2) 6.3i NGDBuild/Spartan-3 - NgdBuild:488 - LVPECL_25 is unsupported (Xilinx Answer 20124)
(SP1) 6.3i NGDBuild - RISE_SLEW and FALL_SLEW are not supported on pad nets (Xilinx Answer 19951)


(SP3) 6.3i PACE - Fatal Error when assigning I/O to the upper right-hand corner of the device (Xilinx Answer 20428)
(SP2) 6.3iPACE - Spartan-3 SSO data is out of synch with the Data Sheet (Xilinx Answer 20126)
(SP1) 6.3i PACE Virtex-4 - Only BANK0-7 are shown in LOC drop-down for Virtex-4 (Xilinx Answer 19952)
(SP1) 6.3i PACE Virtex-4 - Cannot place PPC405_ADV (Xilinx Answer 19954)


(SP3) 6.3i Virtex-II PRO PAR - Placer fails to place GT comps correctly in PCI Express design when timing driven packing is used (Xilinx Answer 20451)
(SP3) 6.3i Virtex-4 PAR - Router fails to route regional clock in PCI design (Xilinx Answer 20452)
(SP3) 6.3i Virtex-4 PAR - Placer fails to correctly place IO related to Channel bonded GT11 comps leading to routing failures (Xilinx Answer 20453)
(SP2) 6.3i Virtex-4 PAR - Placer crash after Phase 1.1 when BUFR used (Xilinx Answer 20177)
(SP2) 6.3i Virtex-4 PAR - Placer is restricting logic driven by BUFR to a single clock region (Xilinx Answer 20178)
(SP2) 6.3i Virtex-4 PAR - PAR crashes in Phase 1.1 after printing the message "At least one regional clock net is impossible to be routed" (Xilinx Answer 20179)
(SP2) 6.3i Virtex-4 PAR - Router is not using a dedicated route from DCM to CCM blocks (PMCD, DPM) (Xilinx Answer 19923)
(SP1) 6.3i PAR - PAR Memory leaks have been fixed for all device architectures (Xilinx Answer 19921)
(SP1) 6.2i Virtex-II PAR - Placer check rejects valid 512x36 BRAM vs. MULT pair (Xilinx Answer 19370)
(SP1) 6.3i Virtex-II PRO - GT11 usage with GT11CLK is failing in PAR with "ERROR:Place:157" (Xilinx Answer 19922)
(SP1) 6.3i Virtex-4 PAR - Router is not using a dedicated route from DCM to CCM blocks (PMCD, DPM) (Xilinx Answer 19923)
(SP1) 6.3i Virtex-4 PAR - The pad report shows "na" value for VCCO in a Bank that contains HSTL_I outputs (Xilinx Answer 19924)
(SP1) 6.3i Virtex-4 PAR - PAR does not correctly handle a design using the IBUFDS_DIFF_OUT primitive (Xilinx Answer 19925)

Project Navigator

(SP3) 6.3 ISE, EDK - Error in ISE instantiation template created for an XMP source - Redeclaration of symbol system (Xilinx Answer 20156)
(SP3) 6.1i ISE - Project Navigator does not identify SysGen DSP hierarchy correctly due to VHDL extended identifiers (Xilinx Answer 20427)
(SP1) 6.2i ISE/EDK - Poor integration of embedded proc into ProjNav using Verilog flow results in "Could not find module/primitive 'myproc'" (Xilinx Answer 19389)
(SP1) 6.3i Install - Is ISE supported on Windows XP Professional Service Pack 2 (SP2)? (Xilinx Answer 19712)


(SP3) 6.3i SimPrim, Timing Simulation - OSERDES writes out "U"s on the output when doing a timing simulation (Virtex-4 / VHDL) (Xilinx Answer 20392)
(SP1) 6.3i SimPrim, Timing Simulation - When I load the SDF for an X_EMAC, multiple errors report: "Instance '/uut/emacs' does not have a generic named 'thold_...". (VHDL, SDF) (Xilinx Answer 19854)
(SP1) 6.2i SP3 SimPrim - Memory collision error message on the VHDL RAM block models might be incomplete (Xilinx Answer 19550)
(SP1) 6.3i SimPrim, Timing Simulation - Compilation of X_IDELAYCTRL causes an "Instance <instance_name> does not have a generic named 'tpd_rst_rdy'" error (VHDL, SDF) (Xilinx Answer 19724)
(SP1) 6.3i SimPrim - TXRUNDISP goes to X when a timing simulation is performed with the GT10 model (Xilinx Answer 19855)


(SP2) Spartan-3L - How do I target a Spartan-3 low power device? (Xilinx Answer 20072)
(SP2) Virtex-E/Spartan-IIE - DLLIOB buffer does not work correctly when requiring VREF (Xilinx Answer 20075)

Speed Files

(SP3) 6.3i Speed File/Timing - What changed in Virtex-II Pro 1.90 version? (Xilinx Answer 20426)
(SP3) 6.3 Speed File/Timing - What has changed in the Virtex-4 version 1.50 of the Speed File? (Xilinx Answer 20422)
(SP3) 6.3i Speed File/Timing - What has changed in Spartan-3 version 1.35 of the Speed File? (Xilinx Answer 20423)
(SP1) 6.3i Speed Files/Timing/Simulation Virtex-4 - Timing Analysis and SDF do not match for clock pad delay Tiopi (Xilinx Answer 19956)
(SP1) 6.3i Speed Files/Timingv Virtex-II Pro X - GT10 parameters changed (Xilinx Answer 19957)
(SP1) 6.3i Speed Files/Timing Virtex-4 - Updated GT11 Setup and Holds times (Xilinx Answer 19958)
(SP1) 6.3i Speed FIle/Timing Virtex-4 - GT11 speed values need updating (Xilinx Answer 19960)

Timing Analyzer

(SP2) 6.3i Timing Analyzer/TRCE - "WARNING:Timing:2751 - The clock refclk_buf has a period... is an invalid warning" (Xilinx Answer 20127)
(SP2) 6.3i Timing/Virtex-IIPro/Virtex-4 - Timing delays associated with PowerPC 405D are incorrect values (Xilinx Answer 20128)
(SP1) 6.2i Timing Analyzer - Report shows a hold time violation that does not exist (Xilinx Answer 19961)
(SP1) 6.2i Timing Analyzer - Runs out of memory when analyzing post MAP NCD (Xilinx Answer 19962)


(SP2) 6.3i UniSim, Simulation - CLKFX of the DCM does not restart after applying reset after the CLKIN is stopped (VHDL) (Xilinx Answer 20087)
(SP1) 6.3i UniSim, Simulation - When the ot_en signal is set to 0, the OT signal for the Virtex-4 Monitor does not go Low (Xilinx Answer 19856)
(SP1) 6.3i UniSim, Simulation - When the tap delay of the ISERDES (IDELAY Module) is increased to a large value, the IDELAY module begins to swallow small input pulses to the ISERDES (VHDL) (Xilinx Answer 19857)
(SP1) 6.3i UniSim, Simulation - The RDY signal toggles after reset on the IDELAYCTRL module (Xilinx Answer 19858)
(SP1) 6.2i UniSim Simulation - ADDRB must be valid for the DOB to be reset on the assertion of the SSRB (Xilinx Answer 19765)
(SP1) 6.3i UniSim, Simulation - DCM does not lock during Verilog simulation when the CLKIN is "1" at time 0 (XAPP677) (Xilinx Answer 19859)
(SP1) 6.3i UniSim, SimPrim, Simulation - Virtex-4 DCM CLKFX is not properly aligned when Locked signal goes High (Xilinx Answer 19861)


(SP1) 6.3i XPower - "WARNING:Power:90 (Power:91) cannot change frequency/activity rate" (Xilinx Answer 19545)


(SP2) 6.1i XST - XST does not respect a hierarchical defparam (Xilinx Answer 19975)
AR# 19959
Date 07/05/2006
Status Archive
Type General Article