The Xilinx Application Note 179 (Xilinx XAPP179), "Using SelectI/O Interfaces in Spartan-II and Spartan-IIE FPGASs" does not include entries for LVDS and LVPECL. What is the recommended maximum number of SSOs for these signals?
Are there SSO guidelines for Spartan-3?
For SSO guidelines, use these substitutions:
Spartan-IIE, LVDS: one output pair = one LVTTL 2mA driver with fast slew rate
Spartan-IIE, LVPECL: one output pair = one LVTTL 24mA driver with fast slew rate
Because the Spartan-3 LVDS driver is very balanced, its switching causes a negligible amount of transient current. As a result, SSOs are typically not a problem in the smaller device/package combinations. However, SSO does become a concern with the larger device/package combinations so please be aware of the SSO guidelines for Spartan-3.
The Spartan-3 SSO guidelines are provided in the "Spartan-3 DC and Switching Characteristic" Data Sheet located at:
Select "Switching Characteristics" -> "Simultaneous Switching Output Guidelines".