We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19981

LogiCORE SPI-4.2 (POS-PHY L4) v7.0 - Release Note and Known Issues for the SPI-4.2 Core


This Release Note is for the SPI-4.2 Core v7.0 released in 6.3i IP Update #3. This Release Note includes the following:

- New Features

- Bug Fixes

- Known Issues

Please see (Xilinx Answer 19939) for the installation instructions and software/tool requirements.

NOTE: This version of the SPI-4.2 (v7.1) is now obsolete, please use the latest version, available from Software Update page:



New Features in v7.0

- Virtex-4 implementation (use the SPI-4.2 Core v6.1 to target Virtex-II or Virtex-II Pro Series)

- Dynamic phase alignment using Virtex-4 embedded resources

- New parameterizable VHDL demonstration testbench

- Greater than 1 Gbps/pin-pair data rates

- Reduced FPGA resource utilization

- Flexible pin-outs

- Support for regional clocks (frees up global clock resources)

Bug Fixes in v7.0

- CR 186301: Overflow flags behave like FULL flags

- Various data sheet updates and corrections

Known Issues

Constraints and Implementation

- Version 7.0 of the SPI-4.2 Core supports only the Virtex-4 family. For Virtex-II and Virtex-II Pro designs, please use the v6.1 SPI-4.2 Core, available from the SPI-4.2 IP lounge.

- Migrating from v6.1 to v7.0. (Xilinx Answer 20036)

- If you are using multiple SPI-4.2 Cores in a single device, please see the "Multiple Core Instantiation" section under the "Special Design Consideration" chapter of the SPI-4.2 User Guide.

- The Regional Clocking option should not be valid when generating a slave Source core. (Xilinx Answer 20001)

- Source core is generated with incorrect clocking option (Global vs Regional). (Xilinx Answer 20318)

- The SPI-4.2 Core signals default to LVDS without the internal device termination. If internal termination is needed, this must be set in the UCF file. (Xilinx Answer 20017)

- TStat[1:0] signals use IBUFGDS when using LVDS status I/O. (Xilinx Answer 19105)

- Synplify fails to synthesize a Verilog wrapper file; an NGDBuild error occurs. (Xilinx Answer 20012)

- When an implementation tool is run with an SPI-4.2 Core, several NGDBuild WARNING and INFO messages are reported. (Xilinx Answer 20000)

- RDClk180_GP, SysClk180_GP, and SysClk180_GBSLV are no longer used. (Xilinx Answer 20023)

- Does the Xilinx SPI-4.2 Core support 622 Mbps? (Xilinx Answer 20024)

- Using regional clocking, a PAR error reports: "Place:120 - There were not enough sites to place all selected components." (Xilinx Answer 20026)

- When I run a PAR of the implementation phase, a "PAR:276" warning appears. (Xilinx Answer 20037)

- Timing Analyzer (TRCE) reports "0 items analyzed". (Xilinx Answer 20040)

- When an SPI-4.2 (PL4) Core is generated through CORE Generator, the following errors occur:

"ERROR:Failure to create .sym symbol file. Cannot post process ASY symbol file. File C:\test\5_2i\pl4_core.asy does not exist."

"ERROR: Did not generate ISE symbol file for core <pl4_core>." (Xilinx Answer 15493)

"ERROR:BitGen:169 - This design contains one or more evaluation cores for which bitstream generation is not supported." (Xilinx Answer 19999)

General Simulation Issues

- Running the gen_sim_model script causes: "WARNING:NgdBuild:440 - FF primitive 'U0/clkdomain0/srts/output_ff' has unconnected net." (Xilinx Answer 20018)

- In timing simulation, TDat and TCtl become "x" right after reset. (Xilinx Answer 20015)

- The Sink core never goes in frame (SnkOof ="1") due to an incorrect training pattern sent from the Xilinx Source core. (Xilinx Answer 20016)

- When I simulate an SPI-4.2 (PL4) Core using NC-Verilog (by Cadence) or VCS (by Synopsys), unusual and inconsistent behavior occurs. (Xilinx Answer 15578)

- When I run timing simulation in Verilog, the Core never goes in frame, signals go "x", or pulses are swallowed. (Xilinx Answer 9872)

- When I simulate the VHDL demonstration testbench, a "value out of range" error occurs. (Xilinx Answer 20028)

- When I simulate an SPI-4.2 Core, multiple warnings appear at the beginning of the simulation. (Xilinx Answer 20030)

- During simulation, warning occurs: "Warning: /X_FF HOLD High VIOLATION ON I WITH RESPECT TO CLK" is reported. (Xilinx Answer 20031)


- When fixed static alignment is used, it is necessary to determine the best IOBDELAY (ISERDES) value or the best DCM setting (PHASE SHIFT) to ensure that the target system contains the maximum system margin and performs across voltage, temperature, and process (multiple chips) variations. (Xilinx Answer 20022)

- An SPI-4.2 (PL4) Sink core with dynamic alignment fails to activate PhaseAlignComplete, goes out of sync, or reports a DIP4 error. (Xilinx Answer 15442)

Other Helpful Answer Records

- How do I edit the SPI-4.2 (PL4) UCF file so that the TSClk is skewed by 180 degrees in the DCM? (Xilinx Answer 15500)

AR# 19981
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked