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AR# 19989

6.3i NetGen, Timing Simulation - Virtex-4 RAMB16 models are showing "Xs" for the clock input when a 200+ MHz clock is sent (pulse-swallowing problem)


Keywords: X_RAMB16, simulate, ports, CLKA, CLKB, valid

Urgency: Standard

General Description:
When I perform a timing simulation with a Virtex-4 RAMB16 model, the CLKA and CLKB input ports are showing "Xs", even though a valid clock is being applied. What is causing this problem?


This issue is caused by a problem with the SDF annotation by NetGen, where the PORT delay of the CLKA and CLKB pins are too large, and this results in the swallowing of the clock pulse.

This issue is currently being investigated.

To work around this issue, follow the steps in (Xilinx Answer 9872).
AR# 19989
Date 11/16/2008
Status Archive
Type General Article
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