UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 19991

8.1i EDK - Data2MEM failure occurs when user programs span multiple PLB BRAM controllers

Description

To extend my code space, I use 3 PLB BRAM controllers contiguously; each connects 128 KB block RAM:

BEGIN plb_bram_if_cntlr

PARAMETER INSTANCE = plb_bram_if_cntlr_1

PARAMETER c_baseaddr = 0xfffa0000

PARAMETER c_highaddr = 0xfffbffff

END

BEGIN plb_bram_if_cntlr

PARAMETER INSTANCE = plb_bram_if_cntlr_2

PARAMETER c_baseaddr = 0xfffc0000

PARAMETER c_highaddr = 0xfffdffff

END

BEGIN plb_bram_if_cntlr

PARAMETER INSTANCE = plb_bram_if_cntlr_3

PARAMETER c_baseaddr = 0xfffe0000

PARAMETER c_highaddr = 0xffffffff

END

However, SimGen fails to make the block RAM initialization. It reports:

"ERROR:Data2MEM:31 - Out of bounds code segment for ram space in 'system_sim.bmm'.

Memory space 'plb_bram_if_cntlr_1_bram' occupies [0xFFFA0000:0xFFFBFFFF]

Code segment #0 occupies [0xFFFA0000:0xFFFC4F57]

ERROR:MDT - Data2Mem generated errors during execution.

ERROR:MDT - Error creating memory initialization files."

Solution

If every section of the software (data, text, bss, etc.) is smaller than 128 KB, then you can use a linker script. (See (Xilinx Answer 16536) for more information.) Otherwise, you can use the following procedures to work around this issue:

1. In XPS, do a "clean all".

2. From the main menu, click Tools -> Generate bitstream (not "Update bitstream").

3. Write a dummy program that is small enough to be covered by a single block RAM controller, and put it in a separate s/w project (e.g., call it "dummy").

4. Enable "update bitstream" for s/w project "dummy".

5. Generate libraries and compile "dummy".

6. Select Tools ->"Generate simulation HDL files".

7. Under your project directory, copy the "simulation" directory to another directory (e.g., "sim").

8. Hand-edit "simulation/behavioral/system_sim.bmm" to put all the BUS BLOCKs into a single large ADDRESS BLOCK. Remember to change the address range near the top to cover the whole desired range. Remove other ADDRESS BLOCKs.

9. Change the active s/w project to your real application project (e.g., MyApps). Activate "Update bitstream" for MyApps.

10. Compile MyApps.c.

11. Launch a xgywin shell and run the following commands:

cd simulation/behavioral

data2mem -bm system_sim.bmm -bd <absolute_path_to_MyApps_elf>/executable.elf tag plb_bram_if_cntlr_1_bram -u -o u tmpucf.ucf

xilperl <Your_EDK_install_dir>/bin/nt/ucf2vhdl.pl tmpucf.ucf system_init.vhd system system_conf vhdl

NOTE: (plb_bram_if_cntlr_1_bram is the name of the ADDRESS BLOCK in your system_sim.bmm).

12. Copy "simulation/behavioral/system_init.vhd" to "sim/behavioral/system_init.vhd".

13. Launch ModelSim outside XPS. (Do not do this within XPS.)

14. From the ModelSim prompt, type:

cd <your_edk_proj_dir>/sim/behavioral

15. Type:

do system.do

16. From this point, follow the normal simulation procedure.

The idea is to generate all the simulation scripts with a dummy program first, hack "system_sim.bmm" to fool Data2BRAM, then manually run Data2MEM and UCF2VHDL to generate the "system_init.vhd" for your real program.

For more information, please refer to (Xilinx Answer 16536).

AR# 19991
Date Created 09/03/2007
Last Updated 12/15/2012
Status Active
Type General Article