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AR# 19997

6.3i UniSim, Simulation - FIFO16 UniSim model is not asserting the ALMOST_EMPTY flag when writing to the FIFO (Verilog)


Keywords: ModelSim, NC-VHDL, Virtex-4

Urgency: Standard

General Description:
When the FIFO16 model is being written to and the ALMOST_EMPTY_OFFSET threshold is met, the ALMOST_EMPTY flag should de-assert. The ALMOST_EMPTY flag is not de-asserting in a Verilog UniSim simulation. Why is this occurring?


This problem has been fixed in the latest 6.3i Service Pack available at:
The first service pack containing the fix is 6.3i Service Pack 3.
AR# 19997
Date 10/16/2008
Status Archive
Type General Article
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