We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20009

Virtex-II Pro RocketIO - What is the latency for the current running disparity to be reflected on TXRUNDISP and RXRUNDISP?


How many clock cycles are needed to produce the current running disparity on the TX and the RX?



For RXRUNDISP, there is no latency for the disparity. The disparity shown on this port is aligned to whatever data bytes are displayed on RXDATA.  



There is a latency between TXDATA and TXRUNDISP as the disparity cannot be known ahead of time. The latency arises due to the data going through the CRC (if enabled) and 8b/10b encoder. It is only after your data bytes have passed through the 8b/10b encoder that TXRUNDISP reflects the running disparity for that particular set of bytes. 


For estimates of the latency, refer to Table 2-6 in the RocketIO Transceiver User Guide. There is probably a clock cycle or two of uncertainty due to phase alignment of clocks and various settings. Simulate the MGT, and then monitor TXRUNDISP to see how many clock cycles later it asserts.

AR# 20009
Date 05/16/2014
Status Archive
Type General Article