Verilog and Synplify are chosen as the "Design Entry" in my CORE Generator project option dialog box. When I run the implementation script, the following NGDBuild error occurs:
"ERROR:NgdBuild:28 - Top-level input design file "<component_name>_top.ngo" cannot be found or created. Please make sure the source file exists and is of a recognized netlist format (e.g., ngo, ngc, edif, edn, or edf)."
If I look at the Synplicity log file in <component_name>/implement/verilog/<component_name>_top/*.srr, it will indicate errors in the "Virtex4.v" file:
"@E: CS219 :"<proj>/implement/verilog/virtex4.v":1:0:1:7|Expecting one of the keywords module, primitive or macromodule
@E:"<proj>/implement/verilog/virtex4.v":1:54:2:6|Unknown escape character ?
@E:"<proj>/implement/verilog/virtex4.v":3:62:3:63|Expecting radix character (one of b, o, h, or d)
@E:"<proj>/implement/verilog/virtex4.v":6:46:6:47|expecting identifier immediately following ba<proj>/ck-quote (`)
@E:"<proj>/implement/verilog/virtex4.v":6:51:6:52|expecting identifier immediately following back-quote (`)"
This issue is fixed in SPI4.2 v7.1 released in IP Update #4.
If you do not have access to v7.1 core:
To work around this problem, change the Synplify project file "synplify_ver.prj" that is generated by CORE Generator.
Change the line:
add_file -verilog "virtex4.v"
add_file -verilog "$LIB/xilinx/virtex4.v"
where "$LIB" is the path to the Synplify libraries directory.
Please see (Xilinx Answer 244) for more information on how to instantiate Xilinx-specific components in Synplify.