We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 20015

LogiCORE SPI-4.2 (POS-PHY L4) v7.0 - In timing simulation, TDat and TCtl become "x" right after reset


General Description:  

When I run timing simulation (post-PAR simulation with SDF), the Source Core SPI-4.2 interface signals TDat_P/N and TCtl_P/N become undefined for several clock cycles (~ 4 TDClk_P cycles) after Reset_n is deasserted. After a few more clock cycles, TDat and TCtl settle to the correct defined value. This problem occurs in both VHDL and Verilog simulations.


This issue is apparent only in timing simulation, and you can safely ignore this behavior as the signals stabilize to the correct value after several TDClk cycles.  


This issue will be resolved in a future software release.

AR# 20015
Date 05/16/2014
Status Archive
Type General Article
Page Bookmarked