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AR# 20016

LogiCORE SPI-4.2 (POS-PHY L4) v7.0 - A Sink core never goes in frame (SnkOof ="1") due to an incorrect training pattern from the Xilinx Source core


General Description:  

When I run a timing simulation (post-PAR simulation files with SDF), the Xilinx SPI-4.2 Source core sends incorrect training patterns. This issue occurs when the simulation files are generated from a Source core that targets 644 Mbps performance.  


When the core is enabled and reset is deasserted, the Source core sends incorrect training patterns. For instance, instead of correct training patterns, following pattern is sent: 


TClk_P: --1--------0--------1--------0--------1--------0--------1---------0--------1--------0--------1--------0---  

TCtl_P : --1--------1--------1--------1--------1--------1--------1---------1--------1--------1--------0--------0---  

TDat_P: 0FFF--0FFF--0FFF--0FFF--0FFF--0FFF--0FFF--0FFF--0FFF--0FFF--1000--1000  



TClk_P: --1--------0--------1--------0--------1--------0--------1---------0--------1--------0--------1--------0---  

TCtl_P : --1--------1--------1--------1--------1--------1--------1---------1--------0--------0--------0--------0---  

TDat_P: F000--F000--F000--F000--F000--F000--F000--F000--EFFF--EFFF--OFFF--OFFF 


The output on the TDat bus seems to indicate that some of the bits on TDat are skewed. This behavior extends beyond the training patterns and effects the transmitted data once the Source core is in frame.


This is due to SimPrim model issue in ISE6.3i, and the issue has been fixed in SimPrim of ISE7.1i. Please update to ISE7.1i. 


Please see (Xilinx Answer 20486) on SPI Core compatibility with ISE7.1i.

AR# 20016
Date 05/16/2014
Status Archive
Type General Article
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